CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

EXPCLK

NCS[5:0]

NMWE

A[27:0]

Consecutive expansion write cycles with minimum wait states

tNCSWR

t8

tADWR

WORD

D[31:0]

t2

BUS HELD

NEXPRDY

t7

t2

WRITE DATA

t5

t6

WRITE DATA

Figure 6-3. Expansion and ROM Write Timing

NOTES:

1) tEXWRT = MAX 70 ns at 18.432 MHz and 120 ns at 13.0 MHz for minimum wait states. This time can be

extended by integer multiples of the clock period (54 ns at 18.432 MHz and 77 ns at 13.0 MHz) by either

driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge

of EXPCLK before the data transfer; if low at this point, the transfer is delayed by one clock period where

EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY but is shown for clarity.

2) Consecutive writes with sequential access enabled are identical except that the sequential access wait state

field is used to determine the number of wait states. No idle cycles are inserted between sequential and non

sequential accesses. In addition, the write data set-up time to falling NMWE (T8) cannot be guaranteed to

be positive in this case; for I/O devices where this would cause a problem, the SQAEN bit should not be set.

September 1997

PRELIMINARY DATA BOOK v2.0

79

ELECTRICAL SPECIFICATIONS

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