CL-PS7111
Low-Power System-on-a-Chip
MCLK
DRA[12:0]
RAS[1:0]
CAS[3:0]
DRAM word read followed by page mode read (MCLK shown for reference only)
ROW
COL
ROW
t9
t10
COL 1
COL 2
COL n
tRAS
tRC
tRP
t12
t11
tCP
tCAS
tCP
D[31:0]
NMOE
1
2
n
NMWE
WORD
WRITE
Figure 6-4. DRAM Read Cycles
80
ELECTRICAL SPECIFICATIONS
September 1997
PRELIMINARY DATA BOOK v2.0