CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

EXPCLK

NCS[5:0]

Consecutive expansion read cycles with minimum wait states

tNCSRD

NMOE

A[27:0]

WORD

D[31:0]

t1

BUS HELD

tPCSRD

t3

t4

DATA IN

tADRD

t3

t4

DATA IN

EXPRDY

t5

t6

Figure 6-1. Expansion and ROM Read Timing

NOTES:

1) tEXRD = maximum 70 ns and 120 ns for minimum wait states and a main oscillator frequency of 18.432 MHz

and 13.0 MHz respectively. This time can be extended by integer multiples of the clock period (54 ns), by

either driving EXPRDY low and or by programming a number of wait states. EXPRDY is sampled on the falling

edge of EXPCLK before the data transfer; if low at this point, the transfer is delayed by one clock period where

EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state

field is used to determine the number of wait states, and no idle cycles are inserted between successive non

sequential ROM/expansion cycles. This improves performance, so the SQAEN should always be set where

possible.

September 1997

PRELIMINARY DATA BOOK v2.0

77

ELECTRICAL SPECIFICATIONS

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