CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
Bit Description (cont.)
2 DRAMSZ: Determines width of DRAM memory interface, where 0 = 32-bit DRAM bank; 1 = 16-bit DRAM bank
1 KBD6: The state of this bit determines how many Port A inputs are OR’ed together to create the keyboard interrupt
(and the internal WAKEUP signal if this functionality is enabled by the KBWEN bit). When ‘0’ (the reset state), all 8 Port
A inputs generate a keyboard interrupt. When set high, only Port A bits 0 to 5 generate an interrupt from the keyboard.
It is assumed that the keyboard row lines are connected into Port A.
0 CODECEN: This bit must always be set to ‘1’.
5.39 System Status Flags Register 2 — SYSFLG2
23
UTXFF2
15
7
Reserved
22
21
URXFE2
14
13
Reserved
6
5
CKMODE
20
19
18
17
16
Reserved
12
11
10
9
8
UBUSY2
Reserved
4
3
2
1
0
Reserved
This register is an extension of SYSFLG1, containing status bits for the features new to the CL-PS7111.
Bit Description
23 UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2 bit
rate and line control register. If the FIFO is disabled, this bit is set when the Tx holding register is full. If the FIFO is
enabled, the UTXFF bit is set when the Tx FIFO is full.
22 URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2
bit rate and line control register. If the FIFO is disabled, this bit is set when the Rx holding register contains is empty. If
the FIFO is enabled the URXFE bit is set when the Rx FIFO is empty.
21:12 Reserved
11 UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data. It is guaranteed to remain set
until the complete byte has been sent, including all stop bits.
10:7 Reserved
6 CKMODE: This bit reflects the status of the CLKSEL (Port E bit 2) input, latched during NPOR. When low, the PLL is
running and the chip is operating in 18.432-MHz mode. When high, the chip is operating from an external 13-MHz
clock.
5:0 Reserved
September 1997
PRELIMINARY DATA BOOK v2.0
71
REGISTER DESCRIPTIONS
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