CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

read, becoming valid with the first half word of the address. During the second half word of the address it

is always forced high to meet the requirement of the CL-PS6700.

The PRDY signals from each of the two CL-PS6700 devices are connected to Port B bits 0 and 1, respec-

tively. When the PCMCIA 1 or 2 control bits in the SYSCON2 register are deasserted, these port bits are

available for GPIO. Each PRDY indicates that the CL-PS6700 device driving the PRDY signal is busy

accessing cards if there is no transaction in progress between the CL-PS7111 and CL-PS6700. If a PCM-

CIA access is attempted while the device is busy, the CPU waits for the card to become available, but

DMA for the LCD continues. The CL-PS7111 can access the registers in the CL-PS6700, regardless of

the state of the PRDY signal. If the CL-PS7111 needs to access the PCMCIA card through the

CL-PS6700, it waits until the PRDY signal is high before initiating a transfer request. Once a request is

sent, PRDY indicates whether data is available.

For PCMCIA reads, the PRDY signal from the CL-PS6700 deasserts until the read data is ready, when it

is reasserted and the access completes in the same way as a register access. For a byte access, only

one 16-bit data transfer is required to complete the access. While PRDY is deasserted, the device select

to the CL-PS6700 is deasserted and the main bus released so that DMA for the LCD controller can con-

tinue in the background. The CL-PS7111 will rearbitrate for control of the bus when the PRDY signal is

reasserted to indicate that the read or write transaction can complete. The CPU is always stalled until the

PCMCIA access completes.

A card read operation can be split into a request cycle and a data cycle, or combined into a single

request/data transfer cycle, depending on whether the data requested from the card is available in the

prefetch queue of the selected CL-PS6700.

The request portion of the cycle for a card read is similar to the request phase for a card write previously

described. If the requested data is available in the prefetch queue, the CL-PS6700 asserts PRDY before

the rising edge of the third clock and the CL-PS7111 continues the cycle to read the data. Otherwise,

PRDY is deasserted and the request cycle completes. The CL-PS7111 then allows the DMA controller to

gain control of the bus allowing LCD refreshes to continue. When the CL-PS6700 is ready with the data,

it asserts the PRDY signal. The CL-PS7111 then arbitrates for the bus and once the request is granted

the suspended read cycle resumes. The CL-PS7111 resumes the cycle by asserting the appropriate chip

select and data transfers on the next two clocks.

There is no support within the CL-PS7111 for detecting time-outs. The CL-PS6700 must be programmed

to force the cycle to complete (with invalid data for a read) and generate an interrupt if a read or write

access is timed out. The system software can then determine which access was not successfully com-

pleted by reading the status registers within the CL-PS6700.

DMA is supported only by emulation. That is, the CL-PS6700 will assert its PDREQ (open-drain output,

register external pull-up is required) signal to issue a DMA request. This output will be connected to one

of the CL-PS7111 external interrupts and can be used to interrupt the CPU so software can service the

DMA request under program control.

Either of the two CL-PS6700 devices can generate an interrupt PIRQ (pull-up required on PIRQ). The

PIRQ output is open-drain on the CL-PS6700. If there are two CL-PS6700, they can be wire-OR’ed to the

same interrupt, which can be connected to one of the CL-PS7111 active-low external interrupt sources.

On the receipt of an interrupt, the CPU can read the Interrupt Status registers on the CL-PS6700 to deter-

mine the cause of the interrupt.

All transactions are synchronous to the EXPCLK output from the CL-PS7111 (in 18.432-MHz mode) or

external 13-MHz clock. The RUN signal, or a GPIO signal from CL-PS7111, can be connected to the

September 1997

PRELIMINARY DATA BOOK v2.0

29

FUNCTIONAL DESCRIPTION

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