CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

The system only transitions to the operating state from the standby state if either the NEXTPWR input is

low or the BATOK and NPWRFL inputs are high. This prevents the system attempting to start when the

power supply is inadequate (for example, when the main batteries are flat corresponding to a low level in

NPWRFL or BATOK).

From standby mode, when the WAKEUP signal is applied, the CL-PS7111 initializes into a ready-to-start

state and waits for the first clocks, although the CPU is still held in reset. When the first clock is applied,

there is a delay of about eight clocks before the CPU is first clocked.

Figure 3-4 is a state diagram for the CL-PS7111.

STANDBY

INTERRUPT OR RISING WAKE-UP

WRITE TO STANDBY LOCATION, POWER FAIL

OR USER RESET

OPERATING

INTERRUPT, POWER FAIL

WAKE-UP OR USER RESET

WRITE TO HALT

LOCATION

IDLE

Figure 3-4. State Diagram

3.8 Expansion and ROM Interface

Six separate linear memory or expansion segments are decoded by the CL-PS7111, two of which can be

reserved for two PCMCIA cards each interfacing to the single device CL-PS6700. Each segment is

256 Mbytes and can be interfaced by using a conventional SRAM-like interface. Aside from the six seg-

ments, an additional segment is dedicated for the on-chip 2 Kbytes of SRAM and is fully decoded such

that the addresses for the SRAM do not repeat within the bank. Any of the six segments can be individu-

ally programmed to be 8-, 16-, or 32-bits wide, support Page mode access, and execute from 1–4 wait

states for nonsequential accesses, and 0–3 for burst mode accesses. The zero-wait-state sequential

access feature is designed to support burst mode ROMs; for writable memory devices that use the NMWE

pin, zero-wait-state sequential accesses are not permitted and one wait state is the minimum that should

be programmed in the sequential field of the appropriate MEMCFG register. Bus cycles can also be

extended using the EXPRDY input signal. Page mode access is accomplished by running up to four

accesses together. This can significantly improve bus bandwidth to devices such as ROMs. Sequential

Burst mode access is always faulted (the bus returned to idle) after four accesses, regardless of bus width

to allow DMA and refresh cycles to occur.

Bits 5 and 6 of the SYSCON2 register (see Section 5.38 on page 70) independently enable the interfaces

to the CL-PS6700 (PCMCIA slot drivers). When either of these interfaces are enabled, the corresponding

device select (NCS4 and/or NCS5) becomes dedicated to that CL-PS6700 interface. The state of

SYSCON2[5] determines the function of device select NCS4 (such as the CL-PS6700 interface or stan-

dard device select functionality); SYSCON2[6] controls NCS5 in a similar way. There is no interaction

between these bits.

September 1997

PRELIMINARY DATA BOOK v2.0

25

FUNCTIONAL DESCRIPTION

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