CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

Table 3-3. Peripheral Status in Different Operating States (cont.)

Module

Operating

Idle

Standby

NPOR NURESET

Reset Reset

Interrupt Ctrl

ON

PLL/CLKEN

ON

ON

ON

Reset

Reset

ON

OFF

OFF

OFF

Standby State

The standby state is as if the computer is switched off, there is no display and the main oscillator is shut

down. When the 18.432-MHz mode is selected, the PLL will be shut down. In 13-MHz mode, if the

CLKENSL bit is set low, then the CLKEN signal will be forced low and can disable an external oscillator.

Only the realtime clock is running. The device automatically enters the standby state after power is first

applied or after a system reset. The only exit from the standby state is to the operating state. Before en-

tering the standby state, if external I/O devices (such as CL-PS6700s connected to NCS[4] or NCS[5])

are in use, the software must check for idle before issuing the write to the standby location.

When in standby, all system memory and states are maintained and the system clock is kept current. The

PLL/on-chip oscillator or external oscillator is disabled, and the system is static except for the low-power

(32-kHz) watch crystal oscillator and divider chain to the realtime clock. The RUN signal is driven low. This

signal can be used externally in the system to power down other system modules.

Idle State

The idle state means the device is functioning, but the processor clock is halted while it waits for an event,

such as a key press, to generate an interrupt (a rising edge on the external wake-up pin or a rising edge

on the decode of Port A bits 0–5 or 7). The PLL (in 18.432-MHz mode) or the external 13-MHz clock

source always remains active in the idle state.

Operating State

The operating state is the same as the idle state, except that the processor clock is running.

The device is forced into the standby state at power up or reset by the NPOR signal (called a ‘cold’ reset)

and is the only completely asynchronous reset to the CL-PS7111. The transition to the operating state is

caused by a rising edge on the WAKEUP input signal, or by a rising edge on any of the Port A bits 0–5 or

7 (corresponding to keyboard input). After a cold reset, these are the only possible events for waking up

the device. When entering the standby state from the operating state, the software should leave some

interrupt sources enabled, meaning there is a third possible means of exit from the standby state if an

enabled interrupt is generated (for example, the RTC interrupt). Once self-refresh is enabled for the

DRAMs, any transition to the standby state forces the DRAMs to the self-refresh state before stopping the

PLL or external oscillator.

Once in the operating state, the idle state is entered by writing to a special internal memory location in

the CL-PS7111. If an interrupt or wake-up event occurs, execution of the next instruction continues in the

operating state. A write to the STDBY-WAKEUP internal memory location causes the transition from the

operating state to the standby state.

The system can also be forced into the standby state by hardware if the NPWRFL or NURESET inputs

are forced low. In this case, the transition is synchronized with DRAM cycles to avoid errors or short

cycles.

24

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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