CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PS7111-VC-A Datasheet PDF : 105 Pages
| |||
CL-PS7111
Low-Power System-on-a-Chip
Table 3-2. Endian Functionality and Write Operations (cont.)
Byte Lanes to Memory/Ports/Registers
Address (W/B) Register Contents
Big-endian Memory
Little-endian Memory
Word + 0 (B)
Word + 0 (B)
Word + 0 (B)
11223344
11223344
11223344
a Bold indicates active byte lane.
7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24
44 44
44
44 44 44
44
44
44 44
44
44 44 44
44
44
44 44
44
44 44 44
44
44
3.4 CPU Core
The ARM710a microprocessor is a 32-bit RISC processor with an 8-Kbyte unified cache. This cache has
512 lines of four words arranged as a four-way set association. The cache is directly connected to the
ARM710a microprocessor and caches the virtual address from the processor. The MMU translates the
virtual address into a physical address, and contains a 64-entry TLB (translation look aside buffer) and is
post cache; that is, it only translates external memory references (cache misses) to save power.
The big end bit in the ARM710a control register sets whether the CL-PS7111 treats words in memory as
being stored in big-endian or little-endian format. See Chapters 5 and 11 of the ARM710a Macrocell Data
Sheet for more information on the control register. Memory is viewed as a linear collection of bytes num-
bered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second, and so on. In
the little-endian scheme, the lowest numbered byte in a word is considered to be the least-significant byte
of the word, and the highest numbered byte is the most-significant. Byte 0 of the memory system should
be connected to data lines 7 through 0 (D[7:0]) in this scheme. In the big-endian scheme, the most-sig-
nificant byte of a word is stored at the lowest numbered byte and the least-significant byte is stored at the
highest numbered byte. However, the memory controller of the CL-PS7111 will align the byte lane such
that byte 0 of the memory system may always be connected to D[7:0]. Load and store are the only instruc-
tions affected by the endian functionality. For details on the ARM7 instruction set and CPU architecture,
refer to the ARM710a Macrocell Data Sheet.
3.5 Counters
The CL-PS7111 has two integrated identical timer counters: TC1 and TC2. Each timer counter has an
associated 16-bit read/write data register and control bits in the System Control registers. Each counter
is immediately loaded with the value written to the data register. This value decrements on the second
active clock edge, arriving after the write (after the first complete period of the clock). When the timer
counter underflows (reaches 0) the appropriate interrupt asserts. The timer counters can be read at any
time. The clock source and mode are selected by writing to various bits in the System Control registers.
Clock sources, when running from an 18.432-MHz master clock, are 512kHz and 2 kHz. When using the
13-MHz source, the default frequencies are 541 kHz and 2.115 kHz, respectively. However, in non-PLL
mode, an optional divide by 26 frequency can be generated, thus generating a 500-kHz frequency when
using the 13-MHz source. This divider is enabled by setting OSTB (Operating System Timing in
SYSCON2[12]). When OSTB is set high to select the 500-kHz mode, the 500-kHz frequency is routed to
the timers instead of 512 kHz. This does not affect the frequencies derived from any of the other internal
peripherals.
22
FUNCTIONAL DESCRIPTION
September 1997
PRELIMINARY DATA BOOK v2.0
Share Link: 