CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

For applications that require a small display (such as an alphanumeric one-way pager), on-chip SRAM

can be used as the frame buffer and no external DRAM are required.

The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on reset.

These inputs are latched by the rising edge of NPOR to select the boot option. See Table 3-4 for boot

options.

Table 3-4. Boot Options

PE1

0

0

1

1

PE0

0

1

0

1

Boot Block (NCS[0])

32 bit

8 bit

16 bit

Undefined

3.8.1

CL-PS7111 Boot ROM

The 128 bytes of on-chip Boot ROM contain an instruction sequence to initialize the device, then config-

ures UART1 to receive serial data that will then be placed in the 2-Kbyte on-chip SRAM. Once the down-

load is complete, execution will start at the beginning of the on-chip SRAM. This would allow (for example)

code to be downloaded to program system flash during a product’s manufacturing process. See

Appendix A for details on the ROM Boot Code with comments to describe the stages of execution.

Selection of the Boot ROM option is determined by the state of the MEDCHG pin during power-on reset.

If MEDCHG is high while NPOR is active, then the CL-PS7111 will boot from an external memory device

connected to NCS0 (normal boot mode). If MEDCHG is low, then the boot will be from the on-chip ROM.

Note that in both cases, following the deassertion of power on reset, the CL-PS7111 will be in standby

mode and requires a low-to-high transition on the external wake-up pin to actually start the boot

sequence.

The effect of booting from the on-chip Boot ROM is to reverse the decoding for all device selects internally.

In addition, the sense of bit 1 in the Memory Configuration register is reversed so that 00 = 8 bit access.

Table 3-5 lists the device select address ranges, and Table 3-6 shows the bus width field combinations

that apply after the device has been booted from the on-chip Boot ROM. The control signal for the boot

option is latched by NPOR, which means that the remapping of addresses and bus widths will continue

to apply until NPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM

can be read back from address 0x00000000 and in normal mode of operation the Boot ROM, contents

can be read back from address 0x70000000.

Table 3-5. Device Select Address Ranges After Boot From On-Chip Boot ROM

Address Range (Hexadecimal)

Chip Select

0000.0000 – 0FFF.FFFF

1000.0000 – 1FFF.FFFF

2000.0000 – 2FFF.FFFF

3000.0000 – 3FFF.FFFF

CS[7] (internal only)

CS[6] (internal only)

NCS[5]

NCS[4]

26

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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