CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
The timer counters can operate in two modes: free-running or prescale.
3.5.1
Free-Running Mode
In free-running mode, the counter wraps around to 0xFFFF, then underflows and continues to count down.
Any value written to TC1 or TC2 decrements on the second edge of the selected clock.
3.5.2
Prescale Mode
In prescale mode, the value written to TC1 or TC2 automatically reloads when the counter underflows.
Any value written to TC1 or TC2 decrements on the second edge of the selected clock. This mode can
produce a programmable frequency to drive the buzzer or generate a periodic interrupt.
3.6 Realtime Clock
The CL-PS7111 contains a 32-bit RTC (realtime clock). The RTC is written and read the same as the timer
counters, but is 32 bits wide. The RTC is always clocked at 1 Hz, generated from the 32.768-kHz oscillator.
It also contains a 32-bit output-match register, that can be programmed to generate an interrupt when the
time in the RTC matches a specific time written to this register. The RTC is only reset by an NPOR cold
reset. Because the Realtime Clock Data register is updated from the 1-Hz clock derived from the 32-kHz
source (asynchronous to the main memory system clock) the data register must always be read twice to
ensure a valid and stable reading. This also applies when reading back the RTCDIV field
(SYSFLG1[21:16]), reflecting the status of the six LSBs of the realtime clock counter.
3.7 State Control
The CL-PS7111 supports three operating states: standby, idle, and operating.
In the following descriptions, the RUN/CLKEN pin is used for the run functionality or the CLKEN function-
ality, allowing an external oscillator to be disabled in 13-MHz mode. Either RUN or CLKEN functionality is
selected according to the state of CLKENSL bit (SYSCON2[[13]).
Table 3-3 shows how different modules in CL-PS7111 behave in different states.
Table 3-3. Peripheral Status in Different Operating States
Module
Operating
DRAM Ctrl
ON
UARTs
ON
LCD FIFO
ON
LCD
ON
ADC Interface
ON
Codec
ON
Timers
ON
RTC
ON
DC-to-DC
ON
CPU
ON
Idle
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
Standby
NPOR NURESET
Reset Reset
Self refresh
OFF
Reset
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
Reset
Reset
Reset
Reset
Reset
Reset
ON
Reset
Reset
Self refresh
Reset
Reset
Reset
Reset
Reset
Reset
ON
Reset
Reset
September 1997
PRELIMINARY DATA BOOK v2.0
23
FUNCTIONAL DESCRIPTION
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