CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

Two expansion memory areas are dedicated to supporting up to two CL-PS6700 PCMCIA controllers.

These are selected by NCS[4] and NCS[5] (once enabled by bits 5 and 6 of SYSCON2 respectively). For

efficient, low-power operation, both address and data are carried on the lower 16 bits of the CL-PS7111

data bus. Accesses are initiated by a read or write to or from the area of memory allocated for NCS[4] or

NCS[5]. The memory map within each of these areas is segmented to allow different types of PCMCIA

access to take place for attribute, I/O, and common memory space. The CL-PS6700 internal registers are

memory mapped within the address space as shown in Table 3-7.

Table 3-7. CL-PS6700 Memory Map

Access Type Addresses for CL-PS6700 Interface 1 Addresses for CL-PS6700 Interface 2

Attribute

I/O

Common Memory

CL-PS6700 registers

0x40000000 – 0x43FFFFFF

0x44000000 – 0x47FFFFFF

0x48000000 – 0x4BFFFFFF

0x4C000000 – 0x4FFFFFFF

0x50000000 – 0x53FFFFFF

0x54000000 – 0x57FFFFFF

0x58000000 – 0x5BFFFFFF

0x5C000000 – 0x5FFFFFFF

An access to one of the CL-PS6700 devices will occur according to the following protocol and the timing

in the AC timing specifications in Chapter 6: ELECTRICAL SPECIFICATIONS on page 71. A transaction

is initiated by an access to the NCS4 or NCS5 area. The chip select is asserted and, on the first clock,

the upper 10 bits of the PCMCIA address (along with 6 bits of size, space and slot information) are put

out onto the lower 16 bits of the CL-PS7111 data bus. Only word and single-byte accesses are supported

and the slot field is hardcoded to ‘11’, as the chip selects are used to select the device to be accessed.

This avoids the need to configure the interface during reset. The space field is made directly from the A26

and A27 CPU address bits, according to the decode shown in Table 3-8. The size file is forced to ‘11’ if a

word access is required, or ‘00’ for a byte access. On the second clock cycle, the remaining 16 bits of the

PCMCIA address are multiplexed out onto the lower 16 bits of the data bus. If the transaction selected is

a CL-PS6700 register transaction, or a write to the PCMCIA card (assuming there is space available in

the write buffer) then the access will continue on the following two clock cycles, during which the upper

and lower halves of the word to be read or written will be put onto the lower 16 bits of the main data bus.

Table 3-8. Space Field Decoding

Space Field Value PCMCIA Memory Space

00

Attribute

01

I/O

10

Common Memory

11

CL-PS6700 registers

PCMCIA writes can be posted to the CL-PS6700 device with the same timing as CL-PS6700 internal reg-

ister writes, and are completed by the CL-PS6700 device independent of processor activity. If a posted

write times out or fails to complete, the CL-PS6700 will issue an interrupt. When the write queue is already

full, the PRDY signal deasserts and the transaction waits pending an available slot in the queue. In this

case the CPU waits until the write can be posted successfully.

The ‘ptype’ signal to the CL-PS6700 should be connected to the CL-PS7111 WRITE output. During PCM-

CIA accesses, the polarity of this pin changes and becomes low to signify a write and high to signify a

28

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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