CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

5.2.2 Receive Configuration

After each reset, the CS8900 must be configured

for receive operation. This can be done automat-

ically using an attached EEPROM or by writing

configuration commands to the CS8900’s inter-

nal registers (see Section 3.1). The items that

must be configured include:

• which physical interface to use;

• which types of frames to accept;

• which receive events cause interrupts; and,

• how received frames are transferred.

Configuring the Physical Interface: Configuring

the physical interface consists of determining

which Ethernet interface should be active, and

enabling the receive logic for serial reception.

This is done via the LineCTL register (Register

13) and is described in Table 5.1.

Register 13, LineCTL

Bit Bit Name

Operation

6 SerRxON When set, reception enabled.

8 AUIonly W h e n s e t , AUI s e le c t e d ( ta ke s

precedence over AutoAUI/10BT). When

clear, 10BASE-T selected.

9 AutoAUI/ When set, automatic interface

10BT selection enabled.

E

LoRx Whe n s et , r eceiver squelc h level

Squelch reduced by approximately 6 dB.

Table 5.1. Physical Interface Configuration

Choosing which Frame Types to Accept: The

RxCTL register (Register 5) is used to determine

which frame types will be accepted by the

CS8900 (a receive frame is said to be "accepted"

when the frame is buffered, either on chip or in

host memory via DMA). Table 5.2 describes the

configuration bits in this register. Refer to Sec-

tion 5.3 for a detailed description of Destination

Address filtering.

Register 5, RxCTL

Bit Bit Name

Operation

6 IAHashA When set, Individual Address frames

that pass the hash filter are accepted*.

7 Promis When set, all frames are accepted*.

cuousA

8 RxOKA When set, frames with valid length and

CRC and that pass the DA filter are

accepted.

9 MulticastA When set, Multicast frames that pass

the hash filter accepted*.

A IndividualA When set, frames with DA that matches

the IA at PacketPage base + 0158h are

accepted*.

B BroadcastA When set, all broadcast frames are

accepted*.

C CRCerrorA When set, frames with bad CRC that

pass the DA filter are accepted.

D RuntA when set, frames shorter than 64 bytes

that pass the DA filter are accepted.

E ExtradataA When set, frames longer than 1518

bytes that pass the DA filter are

accepted (only the first 1518 bytes are

buffered).

* Must also meet the criteria programmed into

bits 8, C, D, and E.

Table 5.2. Frame Acceptance Criteria

Selecting which Events Cause Interrupts: The

RxCFG register (Register 3) and the BufCFG

register (Register B) are used to determine which

receive events will cause interrupts to the host

processor. Table 5.3 describes the interrupt en-

able (iE) bits in these registers.

Register 3, RxCFG

Bit Bit Name

Operation

8 RxOKiE When set, there is an interrupt if a

frame is received with valid length and

CRC*.

C CRCerroriE When set, there is an interrupt if a

frame is received with bad CRC*.

D RuntiE When set, there is an interrupt if a

frame is received that is shorter than

64 bytes*.

E ExtradataiE When set, there is an interrupt if a

frame is received that is longer than

1518 bytes*.

* Must also pass the DA filter before there is an

interrupt.

80

DS150PP2

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