CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Basic I/O Mode Transmit

I/O Mode transmit operations occur in the fol-

lowing order (using interrupts):

1. The host bids for storage of the frame by writ-

ing the Transmit Command to the TxCMD

Port (I/O base + 0004h) and the transmit frame

length to the TxLength Port (I/O base +

0006h).

2. The host reads the BusST register (Register

18) to see if the Rdy4TxNOW bit (Bit 8) is

set. To read the BusST register, the host must

first set the PacketPage Pointer at the correct

location by writing 0138h to the PacketPage

Pointer Port (I/O base + 000Ah). It can then

read the BusST register from the PacketPage

Data Port (I/O base + 000Ch). If Rdy4TxNOW

is set, the frame can be written. If clear, the

host must wait for CS8900 buffer memory to

become available. If Rdy4TxiE (Register B,

BufCFG, Bit 8) is set, the host will be inter-

rupted when Rdy4Tx (Register C, BufEvent,

Bit 8) becomes set. If the TxBidErr bit (Regis-

ter 18, BusST, Bit 7) is set, the transmit length

is not valid.

3. Once the CS8900 is ready to accept the frame,

the host executes repetitive write instructions

(REP OUT) to the Receive/Transmit Data Port

(I/O base + 0000h) to transfer the entire frame

from host memory to CS8900 memory.

For a more detailed description of transmit, see

Section 5.7.

Basic I/O Mode Receive

I/O Mode receive operations occur in the follow-

ing order (In this example, interrupts are enabled

to signal the presence of a valid receive frame):

1. A frame is received by the CS8900, triggering

an enabled interrupt.

2. The host reads the Interrupt Status Queue Port

(I/O base + 0008h) and is informed of the re-

ceive frame.

3. The host reads the frame data by executing

repetitive read instructions (REP IN) from the

Receive/Transmit Data Port (I/O base + 0000h)

to transfer the frame from CS8900 memory to

host memory. Preceding the frame data are the

contents of the RxStatus register (PacketPage

base + 0400h) and the RxLength register

(PacketPage base + 0402h).

For a more detailed description of receive, see

Section 5.2.

Accessing Internal Registers

To access any of the CS8900’s internal registers

in I/O Mode, the host must first setup the Packet-

Page Pointer. It does this by writing the

PacketPage address of the target register to the

PacketPage Pointer Port (I/O base + 000Ah). The

contents of the target register is then mapped into

the PacketPage Data Port (I/O base + 000Ch).

If the host needs to access a sequential block of

registers, the MSB of the PacketPage address of

the first word to be accessed should be set to

"1". The PacketPage Pointer will then move to

the next word location automatically, eliminating

the need to setup the PacketPage Pointer between

successive accesses (see Figure 4.4).

Polling the CS8900 in I/O Mode

If interrupts are not used, the host can poll the

CS8900 to check if receive frames are present

and if memory space is available for transmit.

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