CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

4.9.1 Accesses in Memory Mode

The CS8900 allows Read/Write access to the in-

ternal PacketPage memory, and Read access of

the optional Boot PROM. (See Section 3.7 for a

description of the optional Boot PROM.)

A memory access occurs when all of the follow-

ing are true:

2. Check to see if the ELpresent bit (Register

16, SelfST, bit B) is set. This bit indicates

that external logic for the LA bus decode

is present.

3. Set the ELSEL bit of the EEPROM

Command Register to activate the ELCS

pin for use with the external decode circuit.

• The address on the ISA System Address bus

(SA0 - SA19) is within the Memory space

range of the CS8900 or Boot PROM.

• The CHIPSEL input pin is low.

4. Configure the external logic serially.

• the host must write the memory base address

into the Memory Base Address register

(PacketPage base + 002Ch);

• Either the MEMR pin or the MEMW pin is • the host must set the MemoryE bit (Register

low.

17, BusCTL, Bit A); and

4.9.2 Configuring the CS8900 for Memory

Mode

• the host must set the UseSA bit (Register 17,

BusCTL, Bit 9).

There are two different methods of configuring

the CS8900 for Memory Mode operation. One

method allows the CS8900’s internal memory to

be mapped anywhere within the host system’s

24-bit memory space. The other method limits

memory mapping to the first 1 Mbyte of host

memory space.

Limiting Memory Mode to the First 1 Mbyte of

Host Memory Space: Configuring the CS8900 so

that its internal memory can be mapped on;y

within the first 1 Mbyte of host memory space

requires the following:

• the CHIPSEL pin must be tied low;

General Memory Mode Operation: Configuring

the CS8900 so that its internal memory can be

mapped anywhere within host Memory space re-

quires the following:

• a simple circuit must be added to decode the

Latchable Address bus (LA20 - LA23) and

the BALE signal.

• the host must configure the external logic

with the correct address range as follows:

1. Check to see if the INITD bit (Register 16,

SelfST, bit 7) is set, indicating that initial-

ization is complete.

• the ISA-bus SMEMR signal must be con-

nected to the MEMR pin;

• the ISA-bus SMEMW signal must be con-

nected to the MEMW pin;

• the host must write the memory base address

into the Memory Base Address register

(PacketPage base + 002Ch);

• the host must set the MemoryE bit (Register

17, BusCTL, Bit A); and

• the host must clear the UseSA bit (Register

17, BusCTL, Bit 9).

DS150PP2

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