CS8900-CQ 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

3. When switching from byte accesses to word

accesses, a byte access to an even byte address

must be followed by a byte access to an odd-

byte address before the host may execute a

word access (this will re-align the word trans-

fers to even-byte boundaries). On the other

hand, a byte access to an odd-byte address

may be followed by a word access.

Failure to observe these three rules may cause

data corruption.

Transferring Odd-Byte-Aligned Data

Some applications gather transmit data from

more than one section of host memory. The

boundary between the various memory locations

may be either even- or odd-byte aligned. When

such a boundary is odd-byte aligned, the host

should transfer the last byte of the first block to

an even address, followed by the first byte of the

second block to the following odd address. It can

then resume word transfers. An example of this

is shown in Figure 4.3.

Word Transfer

Word Transfer

Word Transfer

Byte Transfer

Byte Transfer

Word Transfer

Word Transfer

First Block of Data

Second Block of Data

Word Transfer

Figure 4.3. Odd-Byte Aligned Data

Random Access to CS8900 Memory

The first 118 bytes of a receive frame held in the

CS8900’s on-chip memory may be randomly ac-

cessed in Memory mode. After the first 118

bytes, only sequential access of received data is

allowed. Either byte or word access is permitted,

as long as all word accesses are executed to

even-byte boundaries.

4.9 Memory Mode Operation

To configure the CS8900 for Memory Mode, the

PacketPage memory must be mapped into a con-

tiguous 4-kbyte block of host memory. The block

must start at an X000h boundary, with the Pack-

etPage base address mapped to X000h. When the

CS8900 comes out of reset, its default configura-

tion is I/O Mode. Once Memory Mode is

selected, all of the CS8900’s registers can be ac-

cessed directly.

In Memory Mode, the CS8900 supports Standard

or Ready Bus cycles without introducing addi-

tional wait states (i.e., IOCHRDY is not

deasserted).

Memory moves can use MOVD (double-word

transfers) as long as the CS8900’s memory base

address is on a double word boundary. Since 286

processors don’t support the MOVD instruction,

word and byte transfers must be used with a 286.

Description Mnemonic Read/Write Location:

PacketPage base

+

Receive RxStatus Read-only

Status

0400h-0401h

Receive RxLength Read-only

Length

0402h-0403h

Receive RxFrame Read-only starts at 0404h

Frame

Transmit

Frame

TxFrame Write-only starts at 0A00h

Table 4.4. Receive/Transmit Memory

Locations

72

DS150PP2

Share Link: