CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

4.9.3 Basic Memory Mode Transmit

Memory Mode transmit operations occur in the

following order (using interrupts):

1.The host bids for storage of the frame by writ-

ing the Transmit Command to the TxCMD

register (memory base + 0144h) and the trans-

mit frame length to the TxLength register

(memory base + 0146h). If the transmit length

is erroneous, the command is discarded and

the TxBidErr bit (Register 18, BusST, Bit 7) is

set.

2.The host reads the BusST register (Register 18,

memory base + 0138h). If the Rdy4TxNOW

bit (Bit 8) is set, the frame can be written. If

clear, the host must wait for CS8900 buffer

memory to become available. If Rdy4TxiE

(Register B, BufCFG, Bit 8) is set, the host

will be interrupted when Rdy4Tx (Register C,

BufEvent, Bit 8) becomes set.

3.Once the CS8900 is ready to accept the frame,

the host executes repetitive memory-to-mem-

ory move instructions (REP MOVS) to

memory base + 0A00h to transfer the entire

frame from host memory to CS8900 memory.

For a more detailed description of transmit, see

Section 5.7.

4.9.4 Basic Memory Mode Receive

Memory Mode receive operations occur in the

following order (interrupts used to signal the

presence of a valid receive frame):

1. A frame is received by the CS8900, triggering

an enabled interrupt.

2. The host reads the Interrupt Status Queue

(memory base + 0120h) and is informed of the

receive frame.

3.The host reads RxStatus (memory base +

0400h) to learn the status of the receive frame.

4.The host reads RxLength (memory base +

0402h) to learn the frame’s length.

5.The host reads the frame data by executing re-

petitive memory-to-memory move instructions

(REP MOVS) from memory base + 0404h to

transfer the entire frame from CS8900 memory

to host memory.

For a more detailed description of receive, see

Section 5.2.

4.9.5 Polling the CS8900 in Memory Mode

If interrupts are not used, the host can poll the

CS8900 to check if receive frames are present

and if memory space is available for transmit.

However, this is beyond the scope of this data

sheet.

4.10 I/O Space Operation

In I/O Mode, PacketPage memory is accessed

through eight 16-bit I/O ports that are mapped

into 16 contiguous I/O locations in the host sys-

tem’s I/O space. I/O Mode is the default

configuration for the CS8900 and is always en-

abled. On power up, the default value of the I/O

base address is set at 300h. (Note that 300h is

typically assigned to LAN peripherals). The I/O

base address may be changed to any available

XXX0h location, either by loading configuration

data from the EEPROM, or during system setup.

Table 4.5 shows the CS8900 I/O Mode mapping:

Receive/Transmit Data Ports 0 and 1

These two ports are used when transferring trans-

mit data to the CS8900 and receive data from the

CS8900. Port 0 is used for 16-bit operations and

74

DS150PP2

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