CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register B, BufCFG

Bit Bit Name

Operation

7 RxDMAiE When set, there is an interrupt if one or

more frames are transferred via DMA.

A RxMissiE When set, there is an interrupt if a

frame is missed due to insufficient

receive buffer space.

B Rx128iE When set, there is an interrupt after the

first 128 bytes of receive data have

been buffered.

D MissOvfloiE When set, there is an interrupt if the

RxMISS counter overflows.

F RxDestiE When set, there is an interrupt after the

DA of an incoming frame has been

buffered.

Table 5.3. Registers 3 & B

Interrupt Configuration

Choosing How to Transfer Frames: The RxCFG

register (Register 3) and the BusCTL register

(Register 17) are used to determine how frames

will be transferred to host memory, as described

in Table 5.4.

Register 3, RxCFG

Bit Bit Name

Operation

7 StreamE When set, StreamTransfer enabled.

9 RxDMAonly When set, DMA slave operation used

for all receive frames.

A AutoRx When set, Auto-Switch DMA enabled.

DMAE

B BufferCRC W h e n s e t, t he r ec e i ved C R C i s

buffered.

Register 17, BusCTL

Bit Bit Name

Operation

B DMABurst When set, DMA operations hold the

bus for up to approximately 28 µs.

When clear, DMA operations are

continuous.

D RxDMAsize When set, DMA buffer size is 64

Kbytes. When clear, DMA buffer size is

16 Kbytes.

Table 5.4. Frame Transfer Method

5.2.3 Receive Frame Pre-Processing

The CS8900 pre-processes all receive frames us-

ing a four step process:

1. Destination Address filtering;

DS150PP2

2. Early Interrupt Generation;

3. Acceptance filtering; and,

4. Normal Interrupt Generation.

Figure 5.3 provides a diagram of frame pre-

processing.

Destination Address Filtering:All incoming

frames are passed through the Destination Ad-

dress filter (DA filter). If the frame’s DA passes

the DA filter, the frame is passed on for further

pre-processing. If it fails the DA filter, the frame

is discarded. See Section 5.3 for a more detailed

description of DA filtering.

Early Interrupt Generation:The CS8900 support

the following two early interrupts that can be

used to inform the host that a frame is being re-

ceived:

• RxDest: The RxDest bit (Register C,

BufEvent, Bit F) is set as soon as the Desti-

nation Address (DA) of the incoming frame

passes the DA filter. If the RxDestiE bit

(Register B, BufCFG, bit F) is set, the

CS8900 generates a corresponding interrupt.

Once RxDest is set, the host is allowed to

read the incoming frame’s DA (the first 6

bytes of the frame).

• Rx128: The Rx128 bit (Register C,

BufEvent, Bit B) is set as soon as the first

128 bytes of the incoming frame have been

received. If the Rx128iE bit (Register B,

BufCFG, bit B) is set, the CS8900 generates

a corresponding interrupt. Once the Rx128

bit is set, the RxDest bit is cleared and the

host is allowed to read the first 128 bytes of

the incoming frame. The Rx128 bit is cleared

by the host reading the BufEvent register

(either directly or through the Interrupt Status

Queue) or by the CS8900 detecting the in-

81

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