CS5376 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376 Datasheet PDF : 122 Pages
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CS5376
Control logic
Data Bus
SPI IRQ
SPI DACK
SPI DREQ
Decimation
Engine
Interface
8-bit shift register
RCH[1:0]
2
SCK2
SO
Pin logic
SI1
SI2
4:1 SI3
SI4
CS0
CS1
Select
CS2
logic
CS3
CS4
Figure 21. Serial Peripheral Interface 2 (SPI 2)
6. SERIAL PERIPHERAL INTERFACE 2
The Serial Peripheral Interface 2 (SPI 2) port is a
master-only SPI port designed to simplify the inter-
face to multiple serial peripherals. A microcontrol-
ler or other SPI bus master need only interface with
the CS5376 SPI 1 port to control up to 20 read-only
or 5 read-write serial slave devices using the SPI 2
port. A system block diagram of the SPI 2 port ap-
pears in Figure 21.
6.1 SPI 2 Pin Descriptions
The SPI 2 port uses a common serial clock (SCK2)
and serial output pin (SO), four serial input pins
(SI1 - SI4), and five chip selects (CS0 - CS4) to
communicate with serial peripherals.
SCK2 - Pin 31
Output clock from the Serial Peripheral Interface 2
port. Maximum rate is 4.096 MHz.
SO - Pin 30
Serial Peripheral Interface 2 data output.
SI1 - SI4 - Pins 26 - 29
Serial Peripheral Interface 2 data inputs.
CS0 - CS4 - Pins 32 - 36
Serial Peripheral Interface 2 chip selects.
6.2 SPI 2 Physical Interface
Because SPI 2 slave devices share a common serial
output pin, the exact number that can be controlled
depends on the number of read-write serial devices
connected. Each read-write serial device must con-
nect to a dedicated chip select pin to ensure write
transactions are not received in error by other serial
devices. The remaining chip select pins can be used
for multiple read-only devices, since separate serial
input pins are available for each.
A chip select pin used for read-only serial devices
can select up to four devices, one for every serial
input pin. A serial transaction to a group of read-
only devices selects all using the common chip-se-
lect pin, and they all receive the read request. Each
DS256PP1
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