CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

Write IIR Coefficients - 0x04

Write ROM Coefficients - 0x05

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Command Transaction

0x04 - IIR Coefficient Write Cmd

IIR Coefficient a11

IIR Coefficient b10

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Burst Transaction

{0x04 - IIR Coefficient Write Cmd}

(IIR Coefficients b11; a22; b21)

(IIR Coefficients a21; b20; b22)

This SPI 1 command uploads custom coefficients

for the two stage IIR filter. The IIR filter consists of

a 1st order IIR stage requiring 3 coefficients (a11,

b10, b11) and a 2nd order IIR stage requiring 5 co-

efficients (a21, a22, b20, b21, b22). A 3rd order IIR

filter is implemented by running both stages. See

“Digital Decimation Filter” on page 53 for more in-

formation about the IIR filters.

The required number of IIR coefficients is fixed, so

the initial SPI command writes the first two coeffi-

cients; (a11, b10). After the initial write, the re-

maining IIR coefficients are written to SPI1DAT1

and SPI1DAT2 using burst transactions; (b11,

a21); (a22, b20); (b21, b22). It’s not necessary to

write the SPI1CMD register during burst transac-

tions, but doing so does not affect operation.

During burst writes, the e2dreq bit in the

SPI1CTRL register indicates when to write new

coefficient values. Immediately after data is writ-

ten, the e2dreq bit is automatically set high. When

e2dreq goes low, the data was accepted and new

data can be written.

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Command Transaction

0x05 - ROM Coefficient Write Cmd

--

--

This SPI 1 command initializes the included coef-

ficients for FIR1, FIR2, and the two stage IIR for

use by the decimation engine. This command only

requires writing the SPI1CMD register; the

SPI1DAT1 and SPI1DAT2 registers are not used.

Write TBS Data - 0x06

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Command Transaction

0x06 - TBS Data Write Cmd

Number of TBS Data

--

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Burst Transaction

{0x06 - TBS Data Write Cmd}

(TBS Data)

(TBS Data)

This SPI 1 command uploads a custom data set for

the test bit stream generator. This command, along

with the ability to program the TBS generator inter-

polation and clock rate, allows the creation of cus-

tom frequency test signals by the test bit stream

generator. See “Test Bit Stream Generator” on

page 81 for more information on generating specif-

ic test frequencies using custom test bit stream data

sets.

The initial SPI command sets the number of TBS

data to be written. After the initial write, TBS data

values are written to SPI1DAT1 and SPI1DAT2

using burst transactions. It’s not necessary to write

the SPI1CMD register during burst transactions,

but doing so does not affect operation.

During burst writes, the e2dreq bit in the SPICTRL

register indicates when to write new coefficient

values. Immediately after data is written, the

DS256PP1

38

Share Link: