CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

E2DREQ Poll Transactions

All SPI 1 command and burst write transactions au-

tomatically use the e2dreq bit in the SPI1CTRL

register to transfer data to the decimation engine.

When the decimation engine clears the e2dreq bit,

the data values were received and another transac-

tion can begin. To ensure the e2dreq bit is cleared

before starting the next transaction, the microcon-

troller can either use single byte read transactions

from the SPI1CTRLM register or can wait a fixed

delay of 1 ms.

To start an e2dreq poll transaction, the SSI signal is

pulled low and the middle byte of the SPI1CTRL

register is read using the SCK1, MOSI, and MISO

pins. The full serial transaction sends the SPI ‘read’

opcode (0x03) with the starting register address

(SPI1CTRLM 0x01) using the SCK1 and MOSI

pins, and receives one data byte using the SCK1

and MISO pins. The returned data byte is the

SPI1CTRLM register value with bit 0 containing

the e2dreq bit (bit 8 of the full SPI1CTRL register).

When completed, the SSI signal is pulled high to

end the transaction.

After reading the e2dreq bit status, the microcon-

troller checks verify it is cleared. If the e2dreq bit is

0, the decimation engine has received the previous

data and is ready for the next transaction. If the

e2dreq bit is 1, the decimation engine has not re-

ceived the previous data and the next transaction

must be delayed. The microcontroller can wait in a

loop between SPI 1 transactions, continuously

reading the e2dreq bit until it is cleared by the dec-

imation engine.

Alternately, the microcontroller can use a fixed de-

lay of 1 ms between transactions to guarantee the

decimation engine received the previous data. A

fixed delay is useful when initialization timing is

not critical, and only adds a nominal setup time for

most systems.

DS256PP1

35

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