CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

transaction, a new serial command transaction can

begin immediately.

To send a serial burst write transaction, the SSI sig-

nal is pulled low and the SPI1DAT1 and

SPI1DAT2 registers are written using the SCK1

and MOSI pins. The full serial transaction sends

the SPI ‘write’ opcode (0x02), the starting register

address (SPI1DAT1H 0x06), and up to six data

bytes. The six data bytes write the additional data

values to the SPI1DAT1 and SPI1DAT2 registers.

When completed, the SSI signal is pulled high and

the SPI 1 port automatically sets the e2dreq bit in

the SPI1CTRL register to send the data values to

the decimation engine.

The decimation engine then uses the SPI1DAT1,

and SPI1DAT2 values to service the current com-

mand. After the decimation engine receives the ad-

ditional data values, it automatically clears the

e2dreq bit in the SPI1CTRL register to indicate the

SPI 1 port is available for the next transaction.

Sending SPI 1 commands to the decimation engine:

1) Initiate a serial command transaction to the SPI1CMD, SPI1DAT1, and SPI1DAT2 registers

to write the SPI 1 command and data values.

A serial command transaction uses the SCK1 and MOSI pins to write the SPI ‘write’ opcode

(0x02), the address of the SPI1CMDH register (0x03), and up to nine data bytes.

2) Delay until the command is received by the decimation engine by polling the SPI1CTRLM

register to check if the e2dreq bit is cleared, or by waiting a fixed delay of 1 ms.

The e2dreq bit is checked using the SCK1, MOSI, and MISO pins by writing the SPI ‘read’

opcode (0x03) and the address of the SPI1CTRLM register (0x01) with the SCK1 and MOSI

pins, and then reading 1 byte of returned data with the SCK1 and MISO pins. The e2dreq bit

is bit 0 of the SPI1CTRLM register (bit 8 of the full SPI1CTRL register).

3) Initiate serial burst transactions, if required by the SPI 1 command, to the SPI1DAT1 and

SPI1DAT2 registers.

A serial burst write transaction uses the SCK1 and MOSI pins to write the SPI ‘write’ opcode

(0x02), the address of the SPI1DAT1H register (0x06), and up to six data bytes.

A serial burst read transaction uses the SCK1, MOSI, and MISO pins by writing the SPI

‘read’ opcode (0x03) and the address of the SPI1DAT1H register (0x06) with the SCK1 and

MOSI pins, and then reading up to six bytes of returned data with the SCK1 and MISO pins.

4) For serial burst write transactions, delay until the data is received by the decimation engine

by polling the SPI1CTRLM register to check if the e2dreq bit is cleared, or by waiting a fixed

delay of 1ms.

Serial burst read transactions do not require a delay after the data read.

DS256PP1

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