CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

Write Register - 0x01

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Command Transaction

0x01 - Register Write Command

Register Address

Register Write Data

This SPI 1 command writes a data value to a deci-

mation engine register. The decimation engine reg-

ister specified in SPI1DAT1 is written with the data

value in SPI1DAT2.

The CS5376 decimation engine registers control

hardware and filtering functions. See “Register

Summary” on page 94 for information about the bit

definitions of the decimation engine registers.

Read Register - 0x02

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Command Transaction

0x02 - Register Read Command

Register Address

--

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Burst Transaction

--

[Register Data]

--

This SPI 1 command reads a data value from a dec-

imation engine register. The value of the decima-

tion engine register specified in SPI1DAT1 is

returned in the SPI1DAT1 register. SPI1DAT2 is

not used by this command.

The CS5376 decimation engine registers control

hardware and filtering functions. See “Register

Summary” on page 94 for information about the bit

definitions of the decimation engine registers.

Write FIR Coefficients - 0x03

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Command Transaction

0x03 - FIR Coefficient Write Cmd

Number of FIR1 Coefficients

Number of FIR2 Coefficients

Register

SPI1CMD

SPI1DAT1

SPI1DAT2

Burst Transaction

{0x03 - FIR Coefficient Write Cmd}

(FIR Coefficient)

(FIR Coefficient)

This SPI 1 command uploads custom coefficients

for the FIR1 and FIR2 filters. A maximum of 255

coefficients can be written for each FIR filter,

though the available decimation engine computa-

tion cycles will limit their practical size. See “Dig-

ital Decimation Filter” on page 53 for more

information about the FIR filters and the cycle lim-

itations of the decimation engine.

The initial SPI command sets the number of FIR1

and FIR2 coefficients to be written. After the initial

write, coefficients for FIR1 and FIR2 are concate-

nated and written to SPI1DAT1 and SPI1DAT2 us-

ing burst transactions. It’s not necessary to write

the SPI1CMD register during burst transactions,

but doing so does not affect operation.

During burst writes, the e2dreq bit in the

SPI1CTRL register indicates when to write new

coefficient values. Immediately after data is writ-

ten, the e2dreq bit is automatically set high. When

e2dreq goes low, the data was accepted and new

data can be written.

DS256PP1

37

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