CL-PS7111
Low-Power System-on-a-Chip
;
ArmMmuCP
CP
0xF
;
ArmMmuId
CN
0x00
;
ArmMmuControl
CN
0x01
ArmMmuControlMmuEnable
EQU
ArmMmuControlAlignFaultEnable EQU
ArmMmuControlCacheEnable
EQU
ArmMmuControlWriteBufferEnable EQU
ArmMmuControl32BitCodeEnable EQU
ArmMmuControl32BitDataEnable EQU
ArmMmuControlMandatory
EQU
ArmMmuControlBigEndianEnable EQU
ArmMmuControlSystemEnable
EQU
ArmMmuControlRomEnable
EQU
;
ArmMmuPageTableBase
CN
0x02
;
ArmMmuDomainAccess
CN
0x03
;
ArmMmuFlushTlb
CN
0x05
;
ArmMmuPurgeTlb
CN
0x06
;
ArmMmuFlushIdc
CN
0x07
0x00000001
0x00000002
0x00000004
0x00000008
0x00000010
0x00000020
0x00000040
0x00000080
0x00000100
0x00000200
;InitialMmuConfig EQU ArmMmuControl32BitCodeEnable
+ArmMmuControl32BitDataEnable +ArmMmuControlMandatory
+ArmMmuControlBigEndianEnable
InitialMmuConfig EQU ArmMmuControl32BitCodeEnable
+ArmMmuControl32BitDataEnable +ArmMmuControlMandatory ;leave as little endian
11/6/96 ks
96
APPENDIX A–BOOT CODE
September 1997
PRELIMINARY DATA BOOK v2.0