CL-PS7111
Low-Power System-on-a-Chip
HwUartControlDataLength6
EQU
0x00020000
HwUartControlDataLength7
EQU
0x00040000
HwUartControlDataLength8
EQU
0x00060000
;
9600baud, 8bits/ch no parity, 1 stop bit
UartValue
EQU HwUartControlRate9600+HwUartControlDataLength8
UartValue_13
EQU HwUartControlRate9600_13+HwUartControlDataLength8
BufferAddress
EQU
snooze buffer
0x10000000
;start address sram
Codeexeaddr
EQU
0x10000000
;
Count
EQU
0x00000800
;2k bytes
startflag
EQU
'<'
endflag
EQU
'>'
CLKMOD
EQU
MHz
0x40;clock mode 1 = 13
;
ARM equates
ArmIrqDisable
ArmFiqDisable
EQU
0x00000080
EQU
0x00000040
ArmUserMode_26
ArmFIQMode_26
ArmIRQMode_26
ArmSVCMode_26
ArmAbortMode_26
ArmUndefMode_26
;
ArmUserMode
ArmFIQMode
ArmIRQMode
ArmSVCMode
ArmAbortMode
ArmUndefMode
ArmMaskMode
EQU
0x00
EQU
0x01
EQU
0x02
EQU
0x03
EQU
0x07
EQU
0x0b
EQU
0x10
EQU
0x11
EQU
0x12
EQU
0x13
EQU
0x17
EQU
0x1B
EQU
0x1F
September 1997
PRELIMINARY DATA BOOK v2.0
95
APPENDIX A–BOOT CODE