CL-PS7111
Low-Power System-on-a-Chip
R
Reset flag (RSTFLG) 51
RTC compare match interrupt (RTCMI) 58
RTC divisor output (RTCDIV) 51
S
Sample clock enable (SMCKEN) 67
Sequential access enable (SQAEN) 54
Synchronous serial interface end-of-transfer inter-
rupt (SSEOTI) 58
T
TC1 under-flow interrupt (TC1OI) 58
TC2 under-flow interrupt (TC2OI) 58
Timer Counter 1 (TC1M) 49
Timer Counter 1 clock source (TC1S) 49
Timer Counter 2 (TC2M) 49
Timer Counter 2 clock source (TC2S) 49
TXFRMEN 67
U
UART framing error (FRMERR) 64
UART overrun error (OVERR) 64
UART parity error (PARERR) 64
UART1 receiver FIFO empty (URXFE1) 51
UART1 transmit FIFO full (UTXFF1) 51
UART1 transmitter busy (UBUSY1) 51
UART2 receiver FIFO empty (URXFE2) 71
UART2 transmit FIFO full (UTXFF2) 71
UART2 transmitter busy (UBUSY2) 71
V
Version ID (VERID) 50
Video buffer size 61
W
Wake-up direct read (WUDR) 52
Wake-up disable (WAKEDIS) 48
Watch dog expired interrupt (WEINT) 59
Word length enable (WRDLEN) 65
100
OVERVIEW
September 1997
PRELIMINARY DATA BOOK v2.0