CL-PS7111
Low-Power System-on-a-Chip
Bit Index
Numerics
64-Hz tick interrupt (TINT) 58
A
AC prescale 60
ADC configuration 67
B
Battery low interrupt (BLINT) 59
Bit rate divisor 66
Bit to drive buzzer (BZTOG) 49
BOOTBIT 51
BREAK 65
BUZ output select (BUZFREQ) 70
Buzzer Drive (BZMOD) 49
C
CKMODE 71
Clear to send (CTS) 51
CLKEN select (CLKENSL) 70
Codec interface enable (CODECEN) 71
Codec interface enable Rx (CDENRX) 48
Codec interface enable Tx (CDENTX) 49
Codec Rx FIFO empty (CRXFE) 51
Codec sound interrupt (CSINT) 59
Codec Tx FIFO full (CTXFF) 51
Cold start flag (CLDFLG) 51
D
Data carrier detect (DCD) 51
Data set ready (DSR) 51
Debug enable (DBGEN) 49
Display ID nibble (DID) 52
DRAM refresh enable (RFSHEN) 57
DRAM refresh rate (RFDIV) 57
DRAMSZ 71
Drive 0 from battery 63
Drive 0 from mains 63
Drive 1 pump ratio 63
E
Even parity (EVENPRT) 65
Expansion clock enable (CLKENB) 54
External expansion clock enable (EXCKEN) 48
External fast interrupt (EXTFIQ) 59
External interrupt input 1 (EINT1) 58
External interrupt input 2 (EINT2) 58
External interrupt input 3 (EINT3) 58
Extra stop (XSTOP) 65
September 1997
PRELIMINARY DATA BOOK v2.0
F
FIFO buffering of Rx and Tx data enable (FIFOEN)
65
Frame length 67
G
Grayscale enable (GSEN) 60
Grayscale mode (GSMD) 60
H
HP SIR protocol encoding enable (SIREN) 48
I
ID 50
Internal UART modem status changed interrupt
(UMSINT) 58
Internal UART receive FIFO half-full interrupt
(URXINT) 58, 72
Internal UART1 transmit FIFO half-empty interrupt
(UTXINT1) 58
Internal UART2 enable (UART2EN) 70
Internal UART2 transmit FIFO half-empty interrupt
(UTXINT2) 72
Inverted NDCDET enable (DCDET) 52
IrDA Tx mode (IRTXM) 48
K
KBD6 71
KBDINT 72
KBWEN 70
L
LCD enable bit (LCDEN) 49
Line length 61
M
Media changed direct read (MCDR) 52
Media changed interrupt (MCINT) 59
Microwire/SPI peripheral clock speed select (AD-
CKSEL) 48
N
New battery flag (NBFLG) 51
O
Operating system timing (OSTB) 70
P
Parity enable (PRTEN) 65
PCMCIA1 70
PCMCIA2 70
Pixel prescale 61
Power fail flag (PFFLG) 51
99
OVERVIEW