CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

6.6.6

Software-Selectable Test Functionality

When bit 11 of the SYSCON register is set HIGH, all internal EPB accesses are output on the main

address and data buses as though they were external accesses to the address space addressed by CS5.

Hence CS5 handles a dual role: It is active as the strobe for internal accesses and for any accesses to

the standard address range for CS5. Additionally, in this mode, the internal signals are multiplexed out of

the device on port pins, as shown in Table 6-5.

Table 6-5. Software Selectable Test Functionality

Signal

CLK

NIRQ

NFIQ

I/O

Pin

Function

O

PE0

Waited clock to CPU

O

PE1

NIRQ interrupt to CPU

O

PE2

NFIQ interrupt to CPU

90

ELECTRICAL SPECIFICATIONS

September 1997

PRELIMINARY DATA BOOK v2.0

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