CS53L32A 查看數據表（PDF） - Cirrus Logic
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CS53L32A Datasheet PDF : 40 Pages
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CS53L32A
MCLK (MHz)
Sample
Rate
(kHz)
128x
HRM
192x
256x*
384x*
256x
384x
BRM
512x
32
4.0960 6.1440 8.1920 12.2880 8.1920 12.2880 16.3840
44.1
5.6448 8.4672 11.2896 16.9344 11.2896 16.9344 22.5792
48
6.1440 9.2160 12.2880 18.4320 12.2880 18.4320 24.5760
64
8.1920 12.2880 16.3840 24.5760
-
-
-
88.2
11.2896 16.9344 22.5792 33.8688
-
-
-
96
12.2880 18.4320 24.5760 36.8640
-
-
-
* MCLKDIV = 1 in Control Port mode or DIV= Hi when in Stand-Alone mode
768x*
24.5760
32.7680
36.8640
-
-
-
1024x*
32.7680
45.1584
49.1520
-
-
-
Table 16. Common Clock Frequencies
Address Bit
MCLK Divide Enable
Serial Control Data I/O
Digital Interface Format
8
AD0/CS (Control Port Mode) (Input) - In Two Wire mode, AD0 is a chip
address bit. CS is used to enable the control port interface in SPI mode.
8
DIV (Stand-Alone Mode) (Input) - When high, the chip will enter High Rate
Mode. When this pin is low, the chip will enter Base Rate Mode.
9
SDA/CDIN (Control Port Mode) (Input/Output) - In Two Wire mode, SDA is
a data I/O line. CDIN is the input data line for the control port interface in SPI
mode.
9
DIF (Stand-Alone Mode) (Input) - The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface
Format.
DIF
DESCRIPTION
0
I2S, up to 24-bit data
1
Left Justified, up to 24-bit data
Table 17. Digital Interface Format - DIF (Stand-Alone Mode)
Serial Control
Interface Clock
Channel Select
10
SCL/CCLK (Control Port Mode) (Input) - Clocks the serial control data into
or from SDA/CDIN/DIF.
10
ChSEL (Stand-Alone Mode) (Input) - The analog data path is determined
by the Channel Select bit. These options are detailed in Table 18.
ChSEL
0
1
DESCRIPTION
Channel 1 directly to A/D
Channel 2 with 32dB of gain
Table 18. Channel Select Options
Anti-Aliasing Capacitors
Positive Voltage
Reference
Analog Inputs
11, 12
13
14, 15, 17, and 18
AFLTR, AFLTL (Output) - Anti-aliasing capacitors for the left and right chan-
nels. An external capacitor is required from AFLTR and AFLTL to ground, as
shown in Figure 5. AFLTR and AFLTL are not intended to supply external
current, and any current drawn from these pins will alter device perfor-
mance.
FILT+ (Output) - Positive reference for internal sampling circuits. An external
capacitor is required from FILT+ to ground, as shown in Figure 6. The rec-
ommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of
PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has
a typical source impedance of 250 kΩ and any current drawn from this pin
will alter device performance.
AIN_R1, AIN_L1, AIN_R2, AIN_L2 (Input) - Channel 1/Channel 2 analog
inputs.
28
DS513F1
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