CS53L32A 查看數據表（PDF） - Cirrus Logic
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CS53L32A Datasheet PDF : 40 Pages
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CS53L32A
7.2 TWO WIRE MODE
In Two Wire mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown in Figure 8. There is no CS pin. Pin AD0 forms the partial
chip address and should be tied to VL or GND as required. The upper 6 bits of the 7 bit address field must
be 001000. To communicate with the CS53L32A the LSB of the chip address field, which is the first byte
sent to the CS53L32A, should match the setting of the AD0 pin. The eighth bit of the address byte is the
R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address
Pointer which selects the register to be read or written. See Section 7.3, Memory Address Pointer (MAP).
If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be
output. Setting the auto increment bit in MAP, allows successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge bit.
Note: The Two-Wire control port mode is compatible with the I2C protocol.
7.3 MEMORY ADDRESS POINTER (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
INCR (Auto MAP Increment Enable)
Default = ‘0’.
0 - Disabled
1 - Enabled
MAP0-2 (Memory Address Pointer)
Default = ‘000’.
3
Reserved
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
DS513F1
31
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