CS53L32A 查看數據表（PDF） - Cirrus Logic
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CS53L32A Datasheet PDF : 40 Pages
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CS53L32A
4.15 LEFT/RIGHT ANALOG GAIN
ADC Independent Analog Gain Control Register (address 06h)
7
LVOL3
6
LVOL2
5
LVOL1
4
LVOL0
3
RVOL3
2
RVOL2
Access:
R/W in Two Wire Mode and write only in SPI.
1
RVOL1
0
RVOL0
Default:
0 - 0 dB (No Gain)
Function:
The level of the left and right analog channels can be adjusted in 1 dB increments as dictated by the
Soft Ramp and Zero Cross bits from 0 to +12 dB when routed through the PGA via the AINMUX bits
in Control Port mode or the CH_SEL pins in Stand-Alone mode. Levels are decoded as shown in
Table 14. Levels above +12 dB are interpreted as +12 dB.
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Volume Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 14. Example Gain Settings
4.16 CLIP DETECTION
Clip Detection Status Register (address 07h)
7
6
5
4
3
RESERVED RESERVED RESERVED RESERVED RESERVED
Access:
Read only in Two Wire Mode and unavailable in SPI.
2
1
0
RESERVED CLIP_L_FLAG CLIP_R_FLAG
Default:
0 - No Clipping Detected
Function:
The Clip Flags indicate when there is an over-range condition anywhere in the CS53L32A internal signal
path. These bits are “sticky”. They constantly monitor the ADC signal path and are set to 1 when an over-
range condition occurs. They are reset to 0 when read.
CLIP_L_FLAG
CLIP_R_FLAG
0
1
Condition
Signal within normal range
Signal is over-range
Table 15. Clip Detection Status Bits
26
DS513F1
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