CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic
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CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
Table 5-1. Internal I/O Memory Locations in Little-Endian Mode (cont.)
Address Name Default R/W Size
Comments
Page
8000.0880– Reserved
–
8000.0FFF
8000.1000 FRBADDR
C
8000.1100 SYSCON2
0
8000.1140 SYSFLG2
0
8000.1240 INTSR2
0
8000.1280 INTMR2
0
8000.1480 UARTDR2
0
8000.14C0 UBRLCR2
0
8000.1700 KBDEOI
–
8000.1840– Reserved
–
BFFF.FFFF
–
– Write has no effect; read is undefined
–
RW 4 LCD Frame Buffer Start Address register
70
RW 16 System Control register 2
70
R
16 System Status Flag register 2
71
R
24 Interrupt Status register 2
72
RW 16 Interrupt Mask register 2
72
RW 8 UART2 Data register
64
RW 32 UART2 Control register
65
–
– Write to clear keyboard interrupt
72
–
– This area contains test registers used during manufactur- –
ing tests. Never attempt to write to these addresses dur-
ing normal operation as this can cause unexpected
behavior. Reads are undefined.
Table 5-2. Port Byte Addresses in Big-Endian Mode
Address
8000.0003
8000.0002
8000.0001
8000.0000
8000.0043
8000.0042
8000.0041
8000.0040
8000.0200
8000.0440
8000.0480
8000.1480
Name Default R/W
PADR
0
RW
PBDR
–
PDDR
PADDR
PBDDR
0
RW
–
0
RW
0
RW
0
RW
–
–
PDDDR
0
RW
DRFPR
0
RW
CODR
0
RW
UARTDR1
0
RW
UARTDR2
0
RW
Size
Comments
8 Port A Data register
8 Port B Data register
8 Reserved
8 Port D Data register
8 Port A Data Direction register
8 Port B Data Direction register
8 Reserved
8 Port D Data Direction register
8 DRAM Refresh Period register
8 Codec Data I/O register
8 UART1 FIFO Data register
8 UART2 FIFO Data register
All internal registers in the CL-PS7111 are reset (cleared to ‘0’) by a system reset (NPOR, NRESET, or
NPWRFL), except for DRFPR, RTCDR, and RTCMR that are only reset when NPOR becomes active.
This ensures that DRAM contents and system time are preserved through a user-reset or power-fail con-
dition.
46
REGISTER DESCRIPTIONS
September 1997
PRELIMINARY DATA BOOK v2.0
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