CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

NPOR (Not Power On Reset)

This is the highest-priority reset signal. When active-low, all storage elements in the CL-PS7111 are reset.

NPOR active forces NSYSRES and NSTBY active. NPOR is only active when the CL-PS7111 first powers

up, not during any other resets. NPOR active clears all flags in the status register, except that CLDFLG

(SYSFLG1[15]) is set.

NSYSRES (Not System Reset)

NSYSRES is generated internally if NPOR, NPWRFL, or NURESET are active. NSYSRES is the second-

highest-priority reset signal and asynchronously resets most internal registers in the CL-PS7111.

NSYSRES active forces NSTBY and RUN low. NSYSRES resets the CL-PS7111, forcing it into the

standby state with no signal from software. The ARM710a is also reset. The memory controller places all

DRAMs in Self-Refresh mode, preserving the contents through a system reset. This is the reason the

DRAM Refresh Period register is not cleared by a system reset.

NSTBY and RUN

The NSTBY and RUN signals are high when the CL-PS7111 is in the operating or idle states, and low

when in standby state. The main system clock is valid when NSTBY is high. The NSTBY signal disables

any peripheral block clocked from the master clock source (that is, everything except for the RTC).

In general, a system reset clears all registers, and NSTBY disables all peripherals that require a main

clock. The following peripherals are disabled by a low level on NSTBY: two UARTs and IrDA SIR encoder,

timer counters, telephony codec, and two SSIs. The following are also disabled in standby mode: LCD

controller and DC-to-DC converter drive.

When operating from an external 13-MHz oscillator, which is disabled in standby mode using the CLKEN

signal (that is, with CLKENSL = 0), the oscillator must be stable within 0.125 sec. from the rising edge of

CLKEN signal.

3.15 Two DC-to-DC Converters

Two programmable duty ratio clock outputs are provided by the CL-PS7111. When the CL-PS7111 is

operating from an 18.432-MHz master clock, these run at a frequency of 96 kHz. When in 13-MHz mode,

these run at 101.6 kHz. Use these signals as drives for DC-to-DC converters in the PSU (power-supply

unit) subsystem. These clocks are enabled by external input pins that are normally connected to the out-

put from comparators monitoring the DC-to-DC converter output. The duty ratio (and the converter on-

time) is programmed from 1-in-16 to 15-in-16. The sense of the DC-to-DC converter drive signal (active-

high or -low) is determined by latching the state of this drive signal during power-on reset (a pull-up resis-

tor on the drive signal results in an active-low drive output and conversely). This allows the DC-to-DC con-

verter to generate either positive or negative voltages.

3.16 Serial Interface

The CL-PS7111 offers the serial interface options as shown in Table 3-15, in addition to the two UARTs.

The codec functionality is available only in 18.432-MHz operation.

Table 3-15. Serial Interface Options

Type

Comments

Transfer Speed

Codec Interface Designed only for use in the 18.432-MHz mode

64 kbps

40

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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