CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

5. REGISTER DESCRIPTIONS

Table 5-1 shows all internal registers in the CL-PS7111, assuming the ARM710a is configured for opera-

tion with a little-endian memory system. Table 5-2 shows the differences that occur for byte accesses to

ports A, B, and D with the ARM710a configured to operate in big-endian mode. All internal registers are

inherently little-endian. Therefore, the system endian functionality affects the addresses required for byte

accesses to internal registers. This results in a reversal of the byte address required to read or write a

particular byte within a register.

There is no effect on the register addresses for word accesses. Bits A0 and A1 of the internal address

bus are only decoded for ports A, B, and D (to allow reads or writes to individual ports). For all other reg-

isters, bits A0 and A1 are not decoded, so that byte reads return the whole register contents to the

CL-PS7111 internal bus, from where the appropriate byte (according to the endian functionality) is read

by the ARM710a. For example, to read data back as a word (irrespective of endian functionality) or a byte

in little-endian mode from the DRFPR (which is only 8-bits wide) requires address 0x8000 0200. However,

a byte read to obtain the register contents in big-endian mode must output address 0x8000 0203. To avoid

the additional complexity, perform all internal register accesses as word operations, except for ports A to

D, which are explicitly designed to operate with byte and word accesses.

8-Kbyte segments of memory in the range 8000.0000–8000.1FFF are reserved for CL-PS7111 internal

use. Accesses in this range do not cause any external bus activity unless debug mode is enabled. Writes

to bits that are not explicitly defined in the internal area are illegal and have no effect. Reads from bits not

explicitly defined in the internal area are legal, but read undefined values. All the internal addresses are

only accessed as 32-bit words, and are always on a word boundary (except for the GPIO Port registers,

which can be accessed as bytes). Address bits in the range A0–A5 are not decoded (except for GPIO

ports A, B, and D). This means each internal register is valid for 64 bytes (for example, the SYSFLG1 reg-

ister appears at locations 8000.0140–8000.017C).

There are some gaps in the register map for backward compatibility with the CL-PS7110 device, but reg-

isters located next to a gap are still decoded only for 64 bytes. The GPIO Port registers are byte-wide, but

can be accessed as a word. These registers additionally decode A0 and A1. All addresses are hexideci-

mal.

Table 5-1. Internal I/O Memory Locations in Little-Endian Mode

Address

8000.0000

8000.0001

8000.0002

8000.0003

8000.0040

8000.0041

8000.0042

8000.0043

8000.0080

Name

PADR

PBDR

–

PDDR

PADDR

PBDDR

–

PDDDR

PEDR

Default R/W Size

Comments

0

RW 8 Port A Data register

0

RW 8 Port B Data register

–

8 Reserved

0

RW 8 Port D Data register

0

RW 8 Port A Data Direction register

0

RW 8 Port B Data Direction register

–

8 Reserved

0

RW 8 Port D Data Direction register

0

RW 3 Port E Data register

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REGISTER DESCRIPTIONS

September 1997

PRELIMINARY DATA BOOK v2.0

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