C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

SFR Definition 14.2. PMU0MD: Power Management Unit Mode

Bit

7

6

5

4

3

2

1

0

Name RTCOE WAKEOE MONDIS

Type R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset 0

0

0

0

0

0

0

0

SFR Page = 0xF; SFR Address = 0xB5

Bit Name

Function

7

RTCOE Buffered SmaRTClock Output Enable.

Enables the buffered SmaRTClock oscillator output on P0.2. Only available on

‘F912 and ‘F902 devices.

0: Buffered SmaRTClock output is not enabled.

1: Buffered SmaRTClock output is enabled.

6 WAKEOE Wakeup Request Output Enable.

Enables the Sleep Mode wake-up request signal on P0.3. Only available on ‘F912

and ‘F902 devices.

0: Wake-up request signal is not enabled.

1: Wake-up request signal is enabled.

5 MONDIS VBAT Supply Monitor Disable.

Writing a 1 to this bit disables the VBAT supply monitor. Writing a 0 to this bit when

the VBAT supply monitor is disabled will trigger a power-on reset. Only available on

‘F912 and ‘F902 devices.

4:0 Unused Unused.

Read = 00000b. Write = Don’t Care.

150

Rev. 1.0

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