C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the

VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the

decoupling capacitance on the VDD/DC+ supply to maintain the supply rail until the capacitors are discharged.

For relatively short sleep intervals, this can result in substantial power savings because the decoupling

capacitance is not continuously charged and discharged.

RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall

below VPOR. The PC counter and all other volatile state information is preserved allowing the device to

resume code execution upon waking up from Sleep mode. The following wake-up sources can be config-

ured to wake the device from sleep mode:

 SmaRTClock Oscillator Fail

 SmaRTClock Alarm

 Port Match Event

 Comparator0 Rising Edge.

The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply

voltage of at least 1.8 V to operate properly. On ‘F912 and ‘F902 devices, the VBAT supply monitor can be

disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is

disabled, all reset sources will trigger a full POR and will re-enable the VBAT supply monitor.

In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep

mode. In order for the MCU to respond to the pin reset event, software must not place the device back into

sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was

due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no

time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor

to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.

14.6. Configuring Wakeup Sources

Before placing the device in a low power mode, one or more wakeup sources should be enabled so that

the device does not remain in the low power mode indefinitely. For Idle Mode, this includes enabling any

interrupt. For Stop Mode, this includes enabling any reset source or relying on the RST pin to reset the

device.

Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up

sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must

be re-enabled each time the device is placed in suspend or sleep mode, in the same write that places the

device in the low power mode.

The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be

awaken from sleep mode. The device must remain awake for more than 15 µs in order for the reset to take

place.

Rev. 1.0

147

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