C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

14.4. Suspend Mode

Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal

oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci-

sion oscillator prior to entering suspend mode. All digital logic (timers, communication peripherals, inter-

rupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs.

The following wake-up sources can be configured to wake the device from suspend mode:

 SmaRTClock Oscillator Fail

 SmaRTClock Alarm

 Port Match Event

 Comparator0 Rising Edge

Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-

up flags. All flags will read back a value of '0' during the first two system clocks following a wake-up from

suspend mode.

In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit

suspend. In order for the MCU to respond to the pin reset event, software must not place the device back

into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-

up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,

there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW

pullup resistor to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.

14.5. Sleep Mode

Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches

the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on the

chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain pow-

ered in two-cell mode and lose their supply in one-cell mode because the dc-dc converter is disabled. In

two-cell mode, only the Comparators remain functional when the device enters sleep mode. All other ana-

log peripherals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering sleep mode.

The system clock source must be set to the low power internal oscillator or the precision oscillator prior to

entering sleep mode.

Note: When exiting sleep mode, 4 NOP instructions should be located immediately after the write to PMU0CF

that placed the device in sleep mode.

Note: If the average active time (between successive entries into Sleep Mode) is less than 1 ms, peripherals

that may cause a wake-up from Sleep Mode (SmaRTClock, Port Match, and Comparator0) or are

enabled or configured in a way which may cause the wake-up flag to be set should be selected as

wake-up sources. If these peripherals are not selected as wake-up sources, then it is recommended to

bypass the Flash one-shot (FLSCL.6=1) before entering into Sleep Mode.

GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,

they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell

mode, the VDD/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage level

and the source and sink current drive capability.

GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port

match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have

in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower the

switching threshold and increase the propagation delay.

C8051F912 and C8051F902 devices support a wakeup request for external devices. Upon exit from sleep

mode, the wake-up request signal is driven high, allowing other devices in the system to wake up from

their low power modes. An example of a system that may benefit from this function is one that uses a high-

power dc-dc converter (>65 mW of output power). The dc-dc converter may be disabled when the system

is asleep, and can be awoken by the wake-up request signal from the MCU. The wakeup request signal is

high when the MCU is awake and low when the MCU is asleep.

146

Rev. 1.0

Share Link: