C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories
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C8051F91X-C8051F90X Datasheet PDF : 318 Pages
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C8051F91x-C8051F90x
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2
Bit
7
Name SLEEP
Type W
Reset 0
6
SUSPEND
W
0
5
CLEAR
W
0
4
RSTWK
R
Varies
3
2
1
0
RTCFWK RTCAWK PMATWK CPT0WK
R/W
R/W
R/W
R/W
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xB5
Bit Name
Description
Write
Read
7
SLEEP Sleep Mode Select
Writing 1 places the
N/A
device in Sleep Mode.
6 SUSPEND Suspend Mode Select
Writing 1 places the
N/A
device in Suspend Mode.
5
CLEAR Wake-up Flag Clear
Writing 1 clears all wake- N/A
up flags.
4 RSTWK Reset Pin Wake-up Flag N/A
Set to 1 if a falling edge
has been detected on
RST.
3 RTCFWK SmaRTClock Oscillator 0: Disable wake-up on
Set to 1 if the SmaRT-
Fail Wake-up Source
SmaRTClock Osc. Fail. Clock Oscillator has failed.
Enable and Flag
1: Enable wake-up on
SmaRTClock Osc. Fail.
2 RTCAWK SmaRTClock Alarm
0: Disable wake-up on
Wake-up Source Enable SmaRTClock Alarm.
and Flag
1: Enable wake-up on
SmaRTClock Alarm.
Set to 1 if a SmaRTClock
Alarm has occurred.
1 PMATWK Port Match Wake-up
0: Disable wake-up on Set to 1 if a Port Match
Source Enable and Flag Port Match Event.
Event has occurred.
1: Enable wake-up on
Port Match Event.
0 CPT0WK Comparator0 Wake-up 0: Disable wake-up on
Set to 1 if Comparator0
Source Enable and Flag Comparator0 rising edge. rising edge has occurred.
1: Enable wake-up on
Comparator0 rising edge.
Notes:
1. Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must
be re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
3. PMU0 requires two system clocks to update the wake-up source flags after waking from Suspend mode. The
wake-up source flags will read ‘0’ during the first two system clocks following the wake from Suspend mode.
Rev. 1.0
149
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