C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories
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C8051F91X-C8051F90X
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C8051F91X-C8051F90X Datasheet PDF : 318 Pages
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C8051F91x-C8051F90x
SFR Definition 13.3. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
Name
BYPASS
Type
R
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit Name
Function
7 Reserved Reserved. Always Write to 0.
6 BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the Flash read time. This setting should be used for oper-
ating frequencies less than 10 MHz.
1: The system clock determines the Flash read time. This setting should be used for
frequencies greater than 10 MHz.
5:0 Reserved Reserved. Always Write to 000000.
Note: Operations which clear the BYPASS bit do not need to be immediately followed by a benign 3-byte instruction
on C8051F912/11/02/01 devices. For code compatibility with C8051F930/31/20/21 devices, a benign 3-byte
instruction whose third byte is a don't care should follow the clear operation. See the C8051F93x-C8051F92x
data sheet for more details.
SFR Definition 13.4. FLWR: Flash Write Only
Bit
7
6
5
4
3
2
1
0
Name
FLWR[7:0]
Type
W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE5
Bit Name
Function
7:0 FLWR[7:0] Flash Write Only.
All writes to this register have no effect on system operation.
142
Rev. 1.0
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