CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

3.4.1 TRST and RESET Pins

As required by the IEEE 1149.1 specification, the

JTAG reset signal, TRST, is independent of the

CS5376 reset signal, RESET. The status of the

TRST pin should be considered during system de-

sign since the TAP controller must be reset before

using the JTAG port.

In systems not using the JTAG test port, the TRST

pin can be connected directly to the RESET pin, or

can be connected to ground. In systems using the

JTAG test port, the TRST and RESET pins should

be independently driven to provide reset capability

during boundry scan.

3.5 Functional Testing

While boundary scan testing gives the ability to

check connections between circuit elements, test-

ing the functionality of the circuit elements them-

selves requires operation of the measurement

channel.

3.5.1 Analog Test DAC

To test the full signal path of a CS5376 system, an

analog test signal should be applied to the modula-

tor inputs. The CS5376 provides a test bit stream

generator that produces a ∆−Σ bit stream suitable

for driving an external test DAC. The analog output

signal from the DAC can be multiplexed to the in-

puts of the measurement channel through relays or

analog multiplexers. Switching the analog test sig-

nal into the measurement channel is typically per-

formed on command from the communication

channel, and requires appropriate control signals to

be defined during system design.

Included as part of the CS5376 test bit stream gen-

erator is an internal feedback path into the digital

filters. This loopback mode provides a fully digital

signal path to test the digital filters and communi-

cations interface. If this is the only test mode used,

no external circuitry is required.

See “Test Bit Stream Generator” on page 81 for

more information about using the test bit stream

generator.

3.5.2 Step Input and Group Delay

Characterizing the step response of a combination

analog and digital measurement channel can be dif-

ficult. A simple method to empirically measure the

step response and group delay through the analog

and digital portions of a CS5376 measurement

channel is to use the time break signal as both a tim-

ing reference and an analog step input. This test re-

quires the system design to include relays or analog

multiplexers to connect the time break signal to the

analog inputs.

See “Time Break Function” on page 75 for more

information about the time break signal.

3.6 System Registers

Several registers are included in the CS5376 for

system information.

The VERSION register (0x2E) in the decimation

engine holds hardware version ID information.

Two registers in the decimation engine, SYSTEM1

and SYSTEM2 (0x2C, 0x2D), are provided for

user defined system information. These are general

purpose registers and will hold any 24-bit data val-

ues written to them.

DS256PP1

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