CS5376
Decimation Engine Registers
Name
CONFIG
RESERVED
GPCFG0
GPCFG1
SPI2CTRL
SPI2CMD
SPI2DAT
RESERVED
FILT_CFG
GAIN1
GAIN2
GAIN3
GAIN4
OFFSET1
OFFSET2
OFFSET3
OFFSET4
TIMEBRK
TBS_CFG
WD_CFG
SYSTEM1
SYSTEM2
VERSION
SELFTEST
Addr.
00
01-0D
0E
0F
10
11
12
13-1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
# Bits
24
24
24
24
24
16
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
Description
Decimation Engine Configuration
Reserved
GPIO[7:0] Direction, Pullup Enable, and Data
GPIO[11:8] Direction, Pullup Enable, and Data
SPI 2 Configuration
SPI 2 Command
SPI 2 Data
Reserved
Filter Configuration
Gain Correction Channel 1
Gain Correction Channel 2
Gain Correction Channel 3
Gain Correction Channel 4
Offset Correction Channel 1
Offset Correction Channel 2
Offset Correction Channel 3
Offset Correction Channel 4
Time Break Counter Configuration
Test Bit Stream Configuration
Watchdog Counter Configuration
User Defined System Register 1
User Defined System Register 2
Hardware Version ID
Self-Test Result Code
SPI 1 Registers
Name
SPI1CTRL
SPI1CMD
SPI1DAT1
SPI1DAT2
Addr.
00 - 02
03 - 05
06 - 08
09 - 0B
Type
R/W
R/W
R/W
R/W
# Bits
8, 8, 8
8, 8, 8
8, 8, 8
8, 8, 8
Description
SPI 1 Control Register
DE <-> SPI 1 Command
DE <-> SPI 1 Data 1
DE <-> SPI 1 Data 2
Figure 6. Decimation Engine and SPI 1 Registers
DS256PP1
12