CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

3. SYSTEM DESIGN

System issues to consider when designing with the

CS5376 include power supply voltages, distribu-

tion of clock and synchronization signals, connec-

tions for EEPROM reprogramming, connections

for boundary scan testing, and extra circuitry re-

quired for functional tests.

3.1 Power Supply Voltages

The CS5376 has three sets of power supply inputs.

Two sets supply power to the I/O pins of the chip

(VDD1, VDD2), and the third set supplies power to

the logic core (VD). The I/O pin power supplies de-

termine the maximum input and output voltages

when interfacing to peripherals, and the logic core

power supply determines the power consumption

of the CS5376.

The voltage choice for a specific power supply de-

pends on two considerations.

1) Available voltages.

It’s simpler to drive all power supplies from a sin-

gle 5 V or 3.3 V supply if it’s already available in

the design. This reduces system cost by eliminating

additional voltage regulators. Power sensitive ap-

plications, however, will require a 3 V supply into

the logic core to minimize power consumption.

2) Required interface voltages.

The two I/O pin power supplies are separated into

a ‘modulator side’ and a ‘microcontroller side’. If

some elements in the design are specified to inter-

face at 5 V and other elements in the design are

specified to interface at another voltage, 3.3 V for

example, the I/O pin power supplies can be inde-

pendently driven to match.

VDD1, GND1 - Pins 54, 53

This I/O pin power supply sets the interface voltage

to the microcontroller, communications channel,

and related peripherals.

Pins driven by the VDD1 power supply are:

• RESET, BOOT, CLK, SYNC, TIMEB

• SSI, SCK1, MOSI, MISO, SINT, SSO

• SDTKI, SDRDY, SDCLK, SDDAT, SDTKO

• GPIO6 - GPIO11

• TRST, TMS, TCK, TDI, TDO

VDD2, GND2 - Pins 11, 25, 24, 38

This I/O pin power supply sets the interface voltage

to the modulators, test DAC, and related peripher-

als.

Pins driven by the VDD2 power supply are:

• MDATA1 - MDATA4, MFLAG1 - MFLAG4

• MCLK, MCLK/2, MSYNC

• SCK2, SI1 - SI4, SO

• TBSCLK, TBSDATA

• GPIO0 - GPIO5

VD, GND - Pins 7, 40, 6, 23, 39

This power supply sets the operational voltage for

the CS5376 logic core. Lowering this voltage to

3 V will minimize power consumption.

3.1.1 Bypass Capacitors

All power supply pins should be bypassed to pro-

vide noise immunity. The bypass capacitors should

be placed as close as possible to the pins of the

CS5376, between the power supply pin and its as-

sociated ground. Suggested values for bypass ca-

pacitors are two parallel caps of 1 µF and 0.01 µF,

or a single cap of 0.1 µF. Bypass capacitors can be

ceramic, tantalum, or any other dielectric type.

3.2 Clock and Synchronization Signals

Many applications of the CS5376 will use a multi-

channel distributed measurement network. To be

useful, data collection must occur with synchro-

nous timing between the measurement channels.

DS256PP1

13

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