CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

Careful design of a clock distribution and synchro-

nization network is crucial for keeping these timing

relationships consistent.

CLK - Pin 58

The CS5376 master clock pin, CLK, has a nominal

input frequency of 32.768 MHz. A slower master

clock can be used if the frequencies from the gen-

erated clocks (MCLK, MCLK/2, SCK1, SCK2,

and TBSCLK) are permitted to run slower. The

CS5376 is a fully static design and can have the

master clock gated off to place the system in a low-

power standby mode.

3.2.1 Master Clock Jitter and Skew

The clock distribution network should supply a

low-jitter, low-skew master clock signal. Clock jit-

ter on the master clock pin, CLK, will result in jitter

on all generated clocks. Jitter on the modulator

clocks (MCLK, MCLK/2) and the test bit stream

clock (TBSCLK) will cause inaccurate conversions

of analog-to-digital and digital-to-analog signals.

Great care should be taken to ensure recovered

clocks have as low jitter as possible.

Clock skew across a measurement network will

cause inaccurate results when reconstructing mea-

surement data during post-processing. By making

measurements at slightly different instants in time,

sensors with clock skew between them cause sig-

nals to appear slower or faster than reality. A good

measurement network design should minimize

clock skew.

3.2.2 Synchronization Jitter and Skew

Similar problems face the distribution of the SYNC

signal. The SYNC input on the CS5376 aligns the

internal clock edges and digital filter phase to the

external system, establishing a precise timing rela-

tionship across the measurement network. Jitter

and skew on the input SYNC signal will result in

phase errors in the CS5376 digital filter data.

The SYNC signal is also used to generate the

MSYNC signal to the modulators. The MSYNC

signal synchronizes the modulator sampling instant

and ensures all modulators are operating with iden-

tical timing across the network. Since the sampling

instant is defined by the MSYNC signal, errors

generating the SYNC signal will result in measure-

ment timing errors by the modulators.

See “System Synchronization” on page 77 for

more information on synchronizing the CS5376

measurement system.

3.3 EEPROM Programming

The CS5376 in stand-alone mode automatically

boots from EEPROM after reset. The configuration

EEPROM holds the commands and data needed to

initialize the system into a fixed operational state.

If stand-alone boot mode is used, the system should

include a way to address the configuration EE-

PROM for in-circuit reprogramming. This can be

performed locally by a technician through a con-

nector, or remotely through the communications

channel.

See “Serial Peripheral Interface 1” on page 21 for

more information about booting the CS5376 using

an EEPROM.

3.4 Boundary Scan Testing

During system design and in the field, in-circuit

testing is a valuable diagnostic tool. The CS5376

JTAG test port enables boundary scan testing by

providing access to all pins via internal boundary

scan cells. To use the JTAG test port, a system de-

sign must provide in-circuit access to the CS5376

JTAG pins (TRST, TMS, TCK, TDI, and TDO).

They can be accessed locally by a technician

through a connector, or remotely through the com-

munications channel.

See “JTAG Test Port (IEEE 1149.1)” on page 89

for more information on the JTAG test port.

DS256PP1

14

Share Link: