QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Quad net

Clock

Logic Cells (Internal)

I/O’s (External)

Figure 17: Global Clock Structure

Table 25: Clock Delay

Parameters

Clock Performance

Global

Dedicated

Clock signal generated internally

1.51 ns (max)

n/a

Clock signal generated externally

2.06 ns (max)

1.73 ns (max)

Table 26: Eclipse Global Clock Performance

Clock Segment

Parameter

Value (ns)

Min

Max

tPGCK

Global clock pin delay to quad net

-

tBGCK

Global clock buffer delay (quad net

to flip flop)

-

1.34

0.56

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

tPGCK

tBGCK

Figure 18: Global Clock Structure Schematic

© 2003 QuickLogic Corporation

•

www.quicklogic.com

•

•

27

•

•

•

Share Link: