QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Recommended Unused Pin Terminations

All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally

using the Configuration Editor. This option is given in the bottom-right corner of the placement

window. To use the Placement Editor, choose ConstraintÆFix Placement in the Option pull-

down menu of SpDE.

The rest of the pins should be terminated at the board level in the manner presented in Table 31.

Signal Name

PLLOUT<x>

IOCTRL<y>

CLK/PLLIN<x>

PLLRST<x>

INREF<y>

Table 31: Recommended Unused Pin Terminations

Recommended Termination

Unused PLL output pins must be connected to either VCC or GND so that their

associated input buffer never floats. Utilized PLL output pins that route the PLL clock

outside of the chip should not be tied to either VCC or GND.

Any unused pins of this type must be connected to either VCC or GND.

Any unused clock pins should be connected to VCC or GND.

If a PLL module is not used, then the associated PLLRST<x> must be connected to

VCC; under normal operation, use it as needed.

If an I/O bank does not require the use of INREF signal the pin should be connected

to GND.

NOTE: x -> number, y -> alphabetical character.

© 2003 QuickLogic Corporation

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