QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

R

CLK

D

tISU

tIHL

Q

tICLK

tIRST

E

tIESU tIEH

Figure 16: Input Register Cell Timings

Table 24: Standard Input Delays

Symbol

Parameter

Standard Input Delays

To get the total input delay add this delay to tISU

tSID(LVTTL)

tSID(LVCMOS2)

LVTTL input delay: Low Voltage TTL for 3.3V applications

LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower

applications

tSID(GTL+)

tSID(SSTL3)

tSID(SSTL2)

GTL+ input delay: Gunning Transceiver Logic

SSTL3 input delay: Stub Series Terminated Logic for 3.3V

SSTL2 input delay: Stub Series Terminated Logic for 2.5V

Value (ns)

Min Max

-

0.34

-

0.42

-

0.68

-

0.55

-

0.61

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26

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© 2003 QuickLogic Corporation

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