QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Symbol

tSWA

tHWA

tSWD

tHWD

tSWE

tHWE

tWCRD

Table 21: RAM Cell Synchronous Write Timing

Parameter: RAM Cell Synchronous Write Timing

Value (ns)

Min

WA setup time to WCLK: the amount of time the Write ADDRESS must be

stable before the active edge of the Write CLOCK

0.675

WA hold time to WCLK: the amount of time the Write ADDRESS must be stable

after the active edge of the Write CLOCK

0

WD setup time to WCLK: the amount of time the Write DATA must be stable

before the active edge of the Write CLOCK

0.654

WD hold time to WCLK: the amount of time the Write DATA must be stable after

the active edge of the Write CLOCK

0

WE setup time to WCLK: the amount of time the Write ENABLE must be stable

before the active edge of the Write CLOCK

0.623

WE hold time to WCLK: the amount of time the Write ENABLE must be stable

after the active edge of the Write CLOCK

0

WCLK to RD (WA=RA): the amount of time between the active Write CLOCK

edge and the moment when the data is available at RD

-

[9:0]

[17:0]

[1:0]

WA

RE

WD

WE

WCL K

RCLK

[9:0]

RA

[17:0]

RD

MOD E

ASYNCRD

RAM Module

Figure 12: RAM Module

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© 2003 QuickLogic Corporation

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