QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Table 22: RAM Cell Synchronous & Asynchronous Read Timing

Symbol

Parameter: RAM Cell Synchronous Read Timing

Value (ns)

Min Max

tSRA

RA setup time to RCLK: time the Read ADDRESS must be stable before the

active edge of the Read CLOCK

0.686

-

tHRA

RA hold time to RCLK: time the Read ADDRESS must be stable after the active

edge of the Read CLOCK

0

-

tSRE

RE setup time to WCLK: time the Read ENABLE must be stable before the

active edge of the Read CLOCK

0.243

-

tHRE

RE hold time to WCLK: time the Read ENABLE must be stable after the active

edge of the Read CLOCK

0

-

tRCRD

RCLK to RD: time between the active Read CLOCK edge and the time when the

data is available at RD

-

4.38

RAM Cell Asynchronous Read Timing

rPDRD

RA to RD: time between when the Read ADDRESS is input and when the DATA

is output

-

2.06

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24

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© 2003 QuickLogic Corporation

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