ISPXPLD5256MX View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
ISPXPLD5256MX
Lattice Semiconductor
ISPXPLD5256MX Datasheet PDF : 92 Pages
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5256MX Logic Signal Connections (Continued)
sysIO Bank LVDS Pair
3
51N
3
51P
0
52N
0
52P
-
-
0
53N
0
53P
0
54N
-
-
0
54P
-
-
0
55N
0
55P
0
56N
0
56P
0
57N
0
57P
0
58N
0
58P
0
59N
0
59P
0
60N
0
60P
-
-
-
-
Primary Macrocell/
Function
F2
F0
G30
G28
GND
G26
G24
G22
VCCO0
G21
GND (Bank 0)
G20
G18
G16/VREF0
G14
G12
G10
G8
G6
G5
G4
G2
G0
VCCO0
GND (Bank 0)
Alternate Outputs
Macrocell 1
Macrocell 2
E1
F1
E0
F0
G31
H31
G30
H30
-
-
G29
H29
G28
H28
G27
H27
-
-
G26
H26
-
-
G25
H25
G24
H24
G3
H3
G2
H2
G23
H23
G22
H22
G21
H21
G20
H20
G19
H19
G18
H18
G1
H1
G0
H0
-
-
-
-
Alternate Input
F3
F1
G31
G29
-
G27
G25
G23
-
-
-
-
G19
G17
G15
G13
G11
G9
G7
-
-
G3
G1
-
-
256 fpBGA
Ball Number
B8
C8
B7
A7
NC
D7
C7
B6
VCCO0
E7
GND (Bank 0)
E6
A6
A5
A4
B5
A3
B4
B3
C5
C6
D5
D6
VCCO0
GND (Bank 0)
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs
55
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