Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
Registered Delays
tS
D-Register Setup
Time, Global Clock
—
tS_PT
D-Register Setup
Time, PT Clock
—
tH
D-Register Hold
Time
—
tCOi
Register Clock to
OSA Time
—
tCESi
Clock Enable Setup
Time
—
tCEHi
Clock Enable Hold
Time
—
D-Input Register
tSIR
Setup Time, Global
—
Clock
D-Input Register
tSIR_PT
Setup Time, PT
—
Clock
D-Input Register
tHIR
Hold Time, Global
—
Clock
D-Input Register
tHIR_PT
Hold Time, PT
—
Clock
Latched Delays
tSL
Latch Setup Time,
Global Clock
—
tSL_PT
Latch Setup Time,
PT Clock
—
tHL
Latch Hold Time
—
tGOi
Latch Gate to OSA
Time
—
tPDLi
Propagation Delay
through Latch to
—
OSA Transparent
Reset and Set Delays
Asynchronous
tSRi
Reset or Set to OSA
—
Delay
Asynchronous
tSRR
Reset or Set
—
Recovery
eXtended Function Routing Delays
Delay through SRP
tROUTEMF
when Implementing
—
Memory Functions
-4
-45
-5
-52
-75
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
0.28 — 0.31 — 0.35 — 0.55 — 0.52 — ns
-0.13 — -0.11 — -0.10 — -0.10 — -0.07 — ns
1.90 — 2.56 — 2.50 — 2.40 — 4.00 — ns
— 0.72 — 1.03 — 0.68 — 0.93 — 1.50 ns
1.07 — 1.20 — 1.33 — 1.33 — 2.00 — ns
0.00 — 0.00 — 0.00 — 0.00 — 0.00 — ns
0.66 — 0.20 — 0.53 — 0.12 — 0.08 — ns
0.42 — 0.37 — 0.34 — 0.34 — 0.22 — ns
0.84 — 1.31 — 1.01 — 1.41 — 2.91 — ns
0.00 — 0.00 — 0.00 — 0.00 — 0.00 — ns
0.18 — 0.00 — 0.00 — 0.00 — 0.00 — ns
0.18 — 0.00 — 0.00 — 0.00 — 0.34 — ns
-0.06 — 0.00 — 0.00 — 0.00 — -0.03 — ns
— 0.07 — 0.08 — 0.08 — 0.08 — 0.13 ns
— 0.52 — 0.58 — 0.65 — 0.65 — 0.97 ns
— 0.23 — 0.26 — 0.29 — 0.29 — 0.43 ns
— 0.42 — 0.47 — 0.53 — 0.55 — 0.79 ns
— 2.00 — 2.25 — 2.51 — 2.61 — 3.76 ns
33