ISPXPLD5256MX View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

MFG CO.

ISPXPLD5256MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Timing Model

The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in

Figure 20 shows the specific delay paths. Once the implementation of a given function is determined either con-

ceptually or from the software report file, the delay path of a function can easily be determined from the timing

model. The Lattice design tools report the timing delays based on the same timing model. Note that internal timing

parameters are for reference only, and are not tested. The external timing parameters are tested and guaranteed

for every device.

Figure 20. ispXPLD 5000MX Timing Model Diagram

From Feedback

tPDb

tIN

IN

t

IOI

tINREG

tINDIO

tROUTE

tROUTEMF

tBLA

tCASC

Memory

Functions

t PTSA

tEXP

tCICOMFB

tCICOMC

tSUM

tPDi

DATA

Q

Feedback

tFBK

tOSA

tBUF

OUT

t

IOO

tEN

tDIS

GCLK

tGCLK _IN

t

IOI

RST

t RST

t

IOI

tGOE

OE

t

IOI

tGCLK

tPLL _DELAY

tPLL _SEC_DELAY

tPTCLK

tBCLK

tPTSR

tBSR

3

CLK, CE and Reset Only

tPTOE

tSPTOE

tGPTOE

Path only available for

FIFO Flags

Some paths not available in memory

mode. Refer to timing tables for details.

C.E.

S/R

MC Reg.

31

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